| commit | 53ef2ec43c1c1eb00b771e17fc157f5bb1103ed5 | [log] [tgz] |
|---|---|---|
| author | Greg Chadwick <gac@lowrisc.org> | Tue Sep 03 14:53:54 2019 +0100 |
| committer | Greg Chadwick <gac@lowrisc.org> | Tue Sep 03 16:19:31 2019 +0100 |
| tree | 1826e1f3fe7e6fc80942dc0fa17c69fc6f136edc | |
| parent | 9614a83991ff65d4adaec454767e7ad057b3f552 [diff] |
Update lowrisc_ibex to lowRISC/ibex@d14312c Ibex top-level interface has changed, single hart_id replaces cluster_id/core_id. Update code from upstream repository https://github.com/lowRISC/ibex.git to revision d14312c3cc47a7d4b34943e4febb96312353b2cc * Replace cluster_id/core_id with hart_id (lowRISC/ibex#29) (Greg Chadwick) * CSR: Access checks on Debug CSRs (Rahul Behl) * [RTL] - Add PMP module (Tom Roberts) * Register file: update comments (Pirmin Vogel) * Controller: change behavior of DRET instruction (Pirmin Vogel) * Update interrupt mode, add debug mode WFI test (lowRISC/ibex#268) (udinator) * Lint: Update Verilator waiver file (Philipp Wagner) * Update google_riscv-dv to 102791d (lowRISC/ibex#266) (taoliug) * Mention CREDITS.md in license header (Philipp Wagner) * Replace author credits in files with CREDITS.md (Philipp Wagner) * Add link to CREDITS.md from README.md (Philipp Wagner) * Add CREDITS.md file (Philipp Wagner) * Integrate risc-v stream generator handshake into Ibex sim flow (lowRISC/ibex#264) (udinator) * Update google_riscv-dv to google/riscv-dv@faddfa4 (lowRISC/ibex#263) (udinator) * Correct a typo in doc/verification.rst (Felix Yan) * Update documentation how to run riscv-compliance (Philipp Wagner) * CI: Run the compliance tests for all ISA variants (Philipp Wagner) * Update google_riscv-dv to e81acc9 (lowRISC/ibex#257) (taoliug) * Make mtvec writable, remove previous workaround (lowRISC/ibex#256) (taoliug) * Test cleanup (lowRISC/ibex#255) (taoliug) * Update google_riscv-dv to 73274f2 (lowRISC/ibex#254) (taoliug) * Consolidate some debug generation options, and make the signature_addr handshake optional (lowRISC/ibex#253) (udinator) * Add more debug tests (lowRISC/ibex#251) (udinator) * src_files.yml: Add ibex_core_tracing.sv (Pirmin Vogel) * ram_1p.sv: Fix rvalid_o generation (Pirmin Vogel) * Remove unused signal data_reg_offset (Ivan Ribeiro) * Add Azure Pipelines build badge to README.md (Philipp Wagner) * CI: Use Azure Pipelines to run lint and some DV (Philipp Wagner) * Update google_riscv-dv to google/riscv-dv@7cce16c (lowRISC/ibex#246) (udinator) * ID stage: rework CSR-related pipeline flushes (Pirmin Vogel) * Adapt Verilator lint waiver (Pirmin Vogel) * Add basic debug test and modify sim flow (lowRISC/ibex#243) (udinator) * [DV] Enable aligned load/store test (lowRISC/ibex#242) (taoliug) * Update google_riscv-dv to 63fa0ca (lowRISC/ibex#241) (taoliug) * Update google_riscv-dv to google/riscv-dv@07599f6 (lowRISC/ibex#240) (udinator) * Fix the verbose logging issue, fix coverage/waveform options (lowRISC/ibex#235) (taoliug) * Update google_riscv-dv to google/riscv-dv@e905e9f (lowRISC/ibex#234) (udinator) * update ibex testbench (lowRISC/ibex#232) (udinator) * update ibex simulation flow (lowRISC/ibex#233) (udinator) * [rtl] Add support for instruction fetch errors (Tom Roberts)
This repository contains hardware, software and utilities written as part of the OpenTitan project. It is structured as monolithic repository, or “monorepo”, where all components live in one repository.
The project contains comprehensive documentation of all IPs and tools. You can either access it online or build it locally by following the steps below.
$ sudo apt install python3 python3-pip $ pip3 install --user -r python-requirements.txt
$ ./util/build_docs.py --preview
This compiles the documentation into ./opentitan-docs and starts a local server, which allows you to access the documentation at http://127.0.0.1:5500.
Have a look at CONTRIBUTING.md for guidelines how to contribute code to this repository.
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).