commit 53b0d4d27472091cb7151a850c2681ef524e6cd7
author Weicai Yang <weicai@google.com> Mon Nov 30 15:28:33 2020 -0800
committer weicaiyang <49293026+weicaiyang@users.noreply.github.com> Tue Dec 01 09:59:04 2020 -0800
tree dfaf386fdbe19f5548bfe7f274a2aa06036d0287
parent 35eabaa9b9b8b7802ed447b6c06fc9c3eeb44457

Run lintpy for reggen/tlgen/topgen

Signed-off-by: Weicai Yang <weicai@google.com>

util/topgen/validate.py

diff --git a/util/topgen/validate.py b/util/topgen/validate.py
index 145d01e..6c5b6c6 100644
--- a/util/topgen/validate.py
+++ b/util/topgen/validate.py
@@ -2,8 +2,8 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 import logging as log
-from enum import Enum
 from collections import OrderedDict
+from enum import Enum
 
 from reggen.validate import check_keys
 
@@ -123,7 +123,8 @@
 eflash_required = {
     'banks': ['d', 'number of flash banks'],
     'pages_per_bank': ['d', 'number of data pages per flash bank'],
-    'program_resolution': ['d', 'maximum number of flash words allowed to program'],
+    'program_resolution':
+    ['d', 'maximum number of flash words allowed to program'],
     'clock_srcs': ['g', 'clock connections'],
     'clock_group': ['s', 'associated clock attribute group'],
     'reset_connections': ['g', 'reset connections'],
@@ -208,7 +209,6 @@
         mem['pgm_resolution_bytes'] = int(self.program_resolution * word_bytes)
 
 
-
 # Check to see if each module/xbar defined in top.hjson exists as ip/xbar.hjson
 # Also check to make sure there are not multiple definitions of ip/xbar.hjson for each
 # top level definition
@@ -293,7 +293,8 @@
     # check clock fields are all there
     ext_srcs = []
     for src in top['clocks']['srcs']:
-        check_keys(src, clock_srcs_required, clock_srcs_optional, {}, "Clock source")
+        check_keys(src, clock_srcs_required, clock_srcs_optional, {},
+                   "Clock source")
         ext_srcs.append(src['name'])
 
     # check derived clock sources
@@ -304,12 +305,15 @@
             ext_srcs.index(src['src'])
         except Exception:
             error += 1
-            log.error("{} is not a valid src for {}".format(src['src'], src['name']))
+            log.error("{} is not a valid src for {}".format(
+                src['src'], src['name']))
 
     # all defined clock/reset nets
     reset_nets = [reset['name'] for reset in top['resets']['nodes']]
-    clock_srcs = [clock['name'] for clock in top['clocks']['srcs'] +
-                  top['clocks']['derived_srcs']]
+    clock_srcs = [
+        clock['name']
+        for clock in top['clocks']['srcs'] + top['clocks']['derived_srcs']
+    ]
 
     # Check clock/reset port connection for all IPs
     for ipcfg in top['module']:
@@ -486,7 +490,8 @@
             else:
                 for domain in reset['domains']:
                     if domain not in top['power']['domains']:
-                        log.error("{} defined invalid domain {}".format(reset['name'], domain))
+                        log.error("{} defined invalid domain {}".format(
+                            reset['name'], domain))
                         error += 1
                         return error
 
@@ -500,7 +505,8 @@
 
             end_point['domain'] = top['power']['default']
         elif end_point['domain'] not in top['power']['domains']:
-            log.error("{} defined invalid domain {}".format(end_point['name'], end_point['domain']))
+            log.error("{} defined invalid domain {}".format(
+                end_point['name'], end_point['domain']))
             error += 1
             return error