commit 5376caa28a37b91ec441edf4ede58085fd9905b9
author Weicai Yang <weicai@google.com> Mon Oct 28 15:28:45 2019 -0700
committer weicaiyang <49293026+weicaiyang@users.noreply.github.com> Fri Nov 01 10:31:27 2019 -0700
tree 2b2920dffcd10892a39ef8a98053b9f33dbd2a01
parent 90ecb990e95707e8d0254128d62db5deec440348

[uart/dv] Adjust timeout and fix xcelium warnings

1. adjust weight and timeout timer to avoid timeout
2. fix a few xcelium warning

hw/ip/uart/dv/env/seq_lib/uart_base_vseq.sv

diff --git a/hw/ip/uart/dv/env/seq_lib/uart_base_vseq.sv b/hw/ip/uart/dv/env/seq_lib/uart_base_vseq.sv
index 4dc6d28..b434bac 100644
--- a/hw/ip/uart/dv/env/seq_lib/uart_base_vseq.sv
+++ b/hw/ip/uart/dv/env/seq_lib/uart_base_vseq.sv
@@ -174,7 +174,7 @@
   // override this function to control RX fifo level
   virtual task rand_read_rx_byte(uint weight_to_skip);
     bit [TL_DW-1:0] rdata;
-    bit [4:0]       rxlvl;
+    int             rxlvl;
 
     randcase
       1: begin // read & check one byte
@@ -232,7 +232,10 @@
   // task to wait for rx fifo not full, will be overriden in overflow test
   virtual task wait_for_rx_fifo_not_full();
     if (ral.ctrl.rx.get_mirrored_value()) begin
-      csr_spinwait(.ptr(ral.status.rxfull), .exp_data(1'b0));
+      `DV_CHECK_MEMBER_RANDOMIZE_FATAL(dly_to_access_fifo)
+      csr_spinwait(.ptr(ral.status.rxfull), .exp_data(1'b0),
+                   .spinwait_delay_ns(dly_to_access_fifo),
+                   .timeout_ns(50_000_000)); // use longer timeout as uart freq is low
     end
     `uvm_info(`gfn, "wait_for_rx_fifo_not_full is done", UVM_HIGH)
   endtask : wait_for_rx_fifo_not_full

hw/ip/uart/dv/env/seq_lib/uart_tx_rx_vseq.sv

diff --git a/hw/ip/uart/dv/env/seq_lib/uart_tx_rx_vseq.sv b/hw/ip/uart/dv/env/seq_lib/uart_tx_rx_vseq.sv
index 900abc7..0bfc293 100644
--- a/hw/ip/uart/dv/env/seq_lib/uart_tx_rx_vseq.sv
+++ b/hw/ip/uart/dv/env/seq_lib/uart_tx_rx_vseq.sv
@@ -192,7 +192,7 @@
                                              dly_to_rx_read dist {
                                                0           :/ 1,
                                                [1:100]     :/ 1,
-                                               [100:10000] :/ 20
+                                               [100:10000] :/ 2
                                              };)
           cfg.clk_rst_vif.wait_clks(dly_to_rx_read);
           wait_when_in_ignored_period(.rx(1));

hw/ip/uart/dv/env/uart_scoreboard.sv

diff --git a/hw/ip/uart/dv/env/uart_scoreboard.sv b/hw/ip/uart/dv/env/uart_scoreboard.sv
index e66f76b..9a76df8 100644
--- a/hw/ip/uart/dv/env/uart_scoreboard.sv
+++ b/hw/ip/uart/dv/env/uart_scoreboard.sv
@@ -347,7 +347,7 @@
           bit [TL_DW-1:0] intr_en = ral.intr_enable.get_mirrored_value();
           do_read_check = 1'b0;
           foreach (intr_exp[i]) begin
-            intr = i; // cast to enum to get interrupt name
+            intr = uart_intr_e'(i); // cast to enum to get interrupt name
             if (cfg.en_cov) begin
               cov.intr_cg.sample(intr, intr_en[intr], intr_exp[intr]);
               cov.intr_pins_cg.sample(intr, cfg.intr_vif.pins[intr]);