commit 53080e4a3dff6a8677e142a3a8223d1c5c1da76c
author Weicai Yang <weicai@google.com> Wed May 18 16:00:56 2022 -0700
committer weicaiyang <49293026+weicaiyang@users.noreply.github.com> Thu May 19 17:03:44 2022 -0700
tree b3fa3f01f1453a401f49f2d216c9750b52f0ca51
parent da52e76d5a4fecafc61aa8bc7256960e46911270

[top, dv] update rv_dm testplan

Signed-off-by: Weicai Yang <weicai@google.com>

hw/top_earlgrey/data/chip_testplan.hjson

diff --git a/hw/top_earlgrey/data/chip_testplan.hjson b/hw/top_earlgrey/data/chip_testplan.hjson
index 1b9b67b..d6a0ad0 100644
--- a/hw/top_earlgrey/data/chip_testplan.hjson
+++ b/hw/top_earlgrey/data/chip_testplan.hjson
@@ -531,10 +531,11 @@
 
             - While Ibex is executing, trigger a debug request by programming `dmcontrol.haltreq`
               via JTAG.
-            - Ibex steps into interactive debug to store a value in SRAM.
-            - Program the program buffer through JTAG with code to store a value in SRAM and return
-              back to normal program execution using dret.
-            - After Ibex jumps back to the program execution, check the stored value in the SRAM.
+            - Ibex steps into interactive debug to execute instructions in SRAM.
+            - Load instruction data into the SRAM via SW. X-ref'ed with chip_sw_sram_execution.
+            - Program the program buffer via JTAG with code to let Ibex jump to the SRAM to
+              execute the instructions.
+            - Verfy that Ibex can fetch and execute the instructions from the SRAM correctly.
             '''
       milestone: V2
       tests: []