add back pressure sequence
diff --git a/hw/ip/hmac/dv/Makefile b/hw/ip/hmac/dv/Makefile
index 4d96fdc..9aabaa8 100644
--- a/hw/ip/hmac/dv/Makefile
+++ b/hw/ip/hmac/dv/Makefile
@@ -34,6 +34,11 @@
UVM_TEST_SEQ = hmac_long_msg_vseq
endif
+ifeq (${TEST_NAME},hmac_back_pressure)
+ UVM_TEST_SEQ = hmac_back_pressure_vseq
+ RUN_OPTS += +zero_delays=1
+endif
+
ifeq (${TEST_NAME},hmac_nist_sha_vectors)
UVM_TEST_SEQ = hmac_nist_vectors_vseq
RUN_OPTS += +nist_vectors_dir=${DV_DIR}/../../../dv/sv/nist_vectors/
diff --git a/hw/ip/hmac/dv/env/seq_lib/hmac_back_pressure_vseq.sv b/hw/ip/hmac/dv/env/seq_lib/hmac_back_pressure_vseq.sv
new file mode 100644
index 0000000..48b42af
--- /dev/null
+++ b/hw/ip/hmac/dv/env/seq_lib/hmac_back_pressure_vseq.sv
@@ -0,0 +1,25 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// This sequence generates back-pressure seq
+// The sequence disabled all the rand delay and optional reg checkings
+
+class hmac_back_pressure_vseq extends hmac_sanity_vseq;
+ `uvm_object_utils(hmac_back_pressure_vseq)
+ `uvm_object_new
+
+ constraint msg_c {
+ msg.size() dist {
+ [65 :999] :/ 1,
+ [1000:3000] :/ 8, // 1KB - 2KB according to SW immediate usage
+ [3001:10_000] :/ 1 // temp set to 10KB as max length, spec max size is 2^64 bits
+ };
+ }
+
+ virtual task pre_start();
+ do_back_pressure = 1'b1;
+ super.pre_start();
+ endtask
+
+endclass : hmac_back_pressure_vseq
diff --git a/hw/ip/hmac/dv/env/seq_lib/hmac_base_vseq.sv b/hw/ip/hmac/dv/env/seq_lib/hmac_base_vseq.sv
index 7a2271f..3de90af 100644
--- a/hw/ip/hmac/dv/env/seq_lib/hmac_base_vseq.sv
+++ b/hw/ip/hmac/dv/env/seq_lib/hmac_base_vseq.sv
@@ -9,7 +9,8 @@
`uvm_object_utils(hmac_base_vseq)
`uvm_object_new
- bit do_hmac_init = 1'b1;
+ bit do_hmac_init = 1'b1;
+ bit do_back_pressure = 1'b0;
rand bit [2:0] wr_size;
rand int wr_addr;
rand bit [3:0] wr_mask;
@@ -125,9 +126,12 @@
bit [7:0] word_unpack[4];
bit [TL_DW-1:0] word;
- bit msg_fifo_full;
- csr_rd(ral.status.fifo_full, msg_fifo_full);
- if (msg_fifo_full) csr_spinwait(.ptr(ral.status.fifo_full), .exp_data(1'b0));
+ if (!do_back_pressure) begin
+ // if not back pressure sequence, wait until fifo_full status cleared then write
+ bit msg_fifo_full;
+ csr_rd(ral.status.fifo_full, msg_fifo_full);
+ if (msg_fifo_full) csr_spinwait(.ptr(ral.status.fifo_full), .exp_data(1'b0));
+ end
if (msg_q.size() < 4) begin
`DV_CHECK_FATAL(randomize(wr_size, wr_addr, wr_mask)
@@ -144,7 +148,9 @@
`uvm_info(`gfn, $sformatf("wr_size = %0h, wr_addr = %0h, wr_mask = %0h, words = 0x%0h",
wr_size, wr_addr, wr_mask, word), UVM_HIGH)
tl_access(.addr(wr_addr), .write(1'b1), .data(word), .mask(wr_mask), .size(wr_size));
- check_status_intr_fifo_full();
+
+ if (!do_back_pressure) check_status_intr_fifo_full();
+ else clear_intr_fifo_full();
end
endtask
@@ -164,6 +170,15 @@
ral.intr_enable.fifo_full.get_mirrored_value()));
endtask
+ // when msg fifo full interrupt is set, this task clears the interrupt
+ // checking the correctness of the fifo full interrupt is done in scb
+ virtual task clear_intr_fifo_full();
+ if (cfg.intr_vif.pins[HmacMsgFifoFull] === 1'b1) begin
+ check_interrupts(.interrupts((1 << HmacMsgFifoFull)),
+ .check_set (ral.intr_enable.fifo_full.get_mirrored_value()));
+ end
+ endtask
+
virtual task compare_digest(bit [31:0] exp_digest[8]);
logic [31:0] act_digest[8];
csr_rd_digest(act_digest);
diff --git a/hw/ip/hmac/dv/env/seq_lib/hmac_sanity_vseq.sv b/hw/ip/hmac/dv/env/seq_lib/hmac_sanity_vseq.sv
index e83fdd0..588d60e 100644
--- a/hw/ip/hmac/dv/env/seq_lib/hmac_sanity_vseq.sv
+++ b/hw/ip/hmac/dv/env/seq_lib/hmac_sanity_vseq.sv
@@ -49,13 +49,13 @@
// msg stream in finished, start hash
trigger_process();
- // read msg fifo length
- rd_msg_length();
-
// wait for interrupt to assert, check status and clear it
wait(cfg.intr_vif.pins[HmacDone] === 1'b1);
check_interrupts(.interrupts((1 << HmacDone)), .check_set(1'b1));
+ // read msg fifo length
+ rd_msg_length();
+
// read digest from DUT
rd_digest();
end
diff --git a/hw/ip/hmac/dv/env/seq_lib/hmac_vseq_list.sv b/hw/ip/hmac/dv/env/seq_lib/hmac_vseq_list.sv
index 6fe41a7..97e901c 100644
--- a/hw/ip/hmac/dv/env/seq_lib/hmac_vseq_list.sv
+++ b/hw/ip/hmac/dv/env/seq_lib/hmac_vseq_list.sv
@@ -6,4 +6,5 @@
`include "hmac_sanity_vseq.sv"
`include "hmac_long_msg_vseq.sv"
`include "hmac_nist_vectors_vseq.sv"
+`include "hmac_back_pressure_vseq.sv"
`include "hmac_csr_vseq.sv"
