| commit | 51ec3894c39b0f48e798e3f370f30d6c0552cbdc | [log] [tgz] |
|---|---|---|
| author | Pirmin Vogel <vogelpi@lowrisc.org> | Tue Jan 12 17:05:57 2021 +0100 |
| committer | Pirmin Vogel <vogelpi@lowrisc.org> | Wed Jan 13 08:39:27 2021 +0100 |
| tree | 7170e1f846d2436a89b4ab20ad5b0d83f3fa7266 | |
| parent | d43704dfd0b8f4d34caa15f76c547b7f69a59efd [diff] |
[prim_sync_reqack_data] Fix SVA checking DST-to-SRC data stability This commit reduces the window during which data must be stable. Since the next REQ only takes 1 SRC clock cycle (and 2 DST clock cycles) to cross over from SRC to DST, it doesn't make sense to check that the data remains stable for 2 SRC clock cycles after the SRC handshake. This resolves lowRISC/OpenTitan#4797. Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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