| commit | 51ea6b8126bfcf1657b239dedecd5c952bbe42b8 | [log] [tgz] |
|---|---|---|
| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Wed Jan 20 10:40:02 2021 +0000 |
| committer | Rupert Swarbrick <rswarbrick@gmail.com> | Wed Jan 20 12:21:04 2021 +0000 |
| tree | ba15561b93cccb4b32e1114b48950b01cb5bbd4b | |
| parent | 1fff985385dda083307777e06154101c7c67a710 [diff] |
[tlul] Explicitly cast between SRAM width and TL width OTBN uses tlul_adapter_sram with a width of 256 bits: more than the TL bus width of 32 bits. This triggers a couple of Verilator warnings caused by width mismatches. This patch makes the "extract bottom bits" and "zero extend" steps explicit. There should be no change in behaviour. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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