[util/reggen] Addressed subword write.
If write size is smaller than the register width, then responses an
error. Previously it raises an error for subword write regardless of the
register width.
For instance, if the CPU writes a byte into a register having smaller
than 8 valid bit, it succeeds. But if register field width is greater
than 8, it returns error now.
Errored write access won't let the register value be written
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv
index 5839b7a..e1b9cb9 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv
@@ -384,4 +384,50 @@
parameter FLASH_CTRL_RD_FIFO_OFFSET = 7'h 50;
parameter FLASH_CTRL_RD_FIFO_SIZE = 7'h 4;
+ // Register Index
+ typedef enum int {
+ FLASH_CTRL_INTR_STATE,
+ FLASH_CTRL_INTR_ENABLE,
+ FLASH_CTRL_INTR_TEST,
+ FLASH_CTRL_CONTROL,
+ FLASH_CTRL_ADDR,
+ FLASH_CTRL_MP_REGION_CFG0,
+ FLASH_CTRL_MP_REGION_CFG1,
+ FLASH_CTRL_MP_REGION_CFG2,
+ FLASH_CTRL_MP_REGION_CFG3,
+ FLASH_CTRL_MP_REGION_CFG4,
+ FLASH_CTRL_MP_REGION_CFG5,
+ FLASH_CTRL_MP_REGION_CFG6,
+ FLASH_CTRL_MP_REGION_CFG7,
+ FLASH_CTRL_DEFAULT_REGION,
+ FLASH_CTRL_MP_BANK_CFG,
+ FLASH_CTRL_OP_STATUS,
+ FLASH_CTRL_STATUS,
+ FLASH_CTRL_SCRATCH,
+ FLASH_CTRL_FIFO_LVL
+ } flash_ctrl_id_e;
+
+ // Register width information to check illegal writes
+ localparam logic [3:0] FLASH_CTRL_PERMIT [19] = '{
+ 4'b 0001, // index[ 0] FLASH_CTRL_INTR_STATE
+ 4'b 0001, // index[ 1] FLASH_CTRL_INTR_ENABLE
+ 4'b 0001, // index[ 2] FLASH_CTRL_INTR_TEST
+ 4'b 1111, // index[ 3] FLASH_CTRL_CONTROL
+ 4'b 1111, // index[ 4] FLASH_CTRL_ADDR
+ 4'b 1111, // index[ 5] FLASH_CTRL_MP_REGION_CFG0
+ 4'b 1111, // index[ 6] FLASH_CTRL_MP_REGION_CFG1
+ 4'b 1111, // index[ 7] FLASH_CTRL_MP_REGION_CFG2
+ 4'b 1111, // index[ 8] FLASH_CTRL_MP_REGION_CFG3
+ 4'b 1111, // index[ 9] FLASH_CTRL_MP_REGION_CFG4
+ 4'b 1111, // index[10] FLASH_CTRL_MP_REGION_CFG5
+ 4'b 1111, // index[11] FLASH_CTRL_MP_REGION_CFG6
+ 4'b 1111, // index[12] FLASH_CTRL_MP_REGION_CFG7
+ 4'b 0001, // index[13] FLASH_CTRL_DEFAULT_REGION
+ 4'b 0001, // index[14] FLASH_CTRL_MP_BANK_CFG
+ 4'b 0001, // index[15] FLASH_CTRL_OP_STATUS
+ 4'b 1111, // index[16] FLASH_CTRL_STATUS
+ 4'b 1111, // index[17] FLASH_CTRL_SCRATCH
+ 4'b 0011, // index[18] FLASH_CTRL_FIFO_LVL
+ };
endpackage
+
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv
index 66cf5f0..69d1495 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv
@@ -37,7 +37,7 @@
logic [DW-1:0] reg_rdata;
logic reg_error;
- logic malformed, addrmiss;
+ logic addrmiss, wr_err;
logic [DW-1:0] reg_rdata_next;
@@ -112,16 +112,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = malformed | addrmiss ;
-
- // Malformed request check only affects to the write access
- always_comb begin : malformed_check
- if (reg_we && (reg_be != '1)) begin
- malformed = 1'b1;
- end else begin
- malformed = 1'b0;
- end
- end
+ assign reg_error = addrmiss | wr_err;
// TODO(eunchan): Revise Register Interface logic after REG INTF finalized
// TODO(eunchan): Make concrete scenario
@@ -2609,16 +2600,16 @@
logic [18:0] addr_hit;
always_comb begin
addr_hit = '0;
- addr_hit[0] = (reg_addr == FLASH_CTRL_INTR_STATE_OFFSET);
- addr_hit[1] = (reg_addr == FLASH_CTRL_INTR_ENABLE_OFFSET);
- addr_hit[2] = (reg_addr == FLASH_CTRL_INTR_TEST_OFFSET);
- addr_hit[3] = (reg_addr == FLASH_CTRL_CONTROL_OFFSET);
- addr_hit[4] = (reg_addr == FLASH_CTRL_ADDR_OFFSET);
- addr_hit[5] = (reg_addr == FLASH_CTRL_MP_REGION_CFG0_OFFSET);
- addr_hit[6] = (reg_addr == FLASH_CTRL_MP_REGION_CFG1_OFFSET);
- addr_hit[7] = (reg_addr == FLASH_CTRL_MP_REGION_CFG2_OFFSET);
- addr_hit[8] = (reg_addr == FLASH_CTRL_MP_REGION_CFG3_OFFSET);
- addr_hit[9] = (reg_addr == FLASH_CTRL_MP_REGION_CFG4_OFFSET);
+ addr_hit[ 0] = (reg_addr == FLASH_CTRL_INTR_STATE_OFFSET);
+ addr_hit[ 1] = (reg_addr == FLASH_CTRL_INTR_ENABLE_OFFSET);
+ addr_hit[ 2] = (reg_addr == FLASH_CTRL_INTR_TEST_OFFSET);
+ addr_hit[ 3] = (reg_addr == FLASH_CTRL_CONTROL_OFFSET);
+ addr_hit[ 4] = (reg_addr == FLASH_CTRL_ADDR_OFFSET);
+ addr_hit[ 5] = (reg_addr == FLASH_CTRL_MP_REGION_CFG0_OFFSET);
+ addr_hit[ 6] = (reg_addr == FLASH_CTRL_MP_REGION_CFG1_OFFSET);
+ addr_hit[ 7] = (reg_addr == FLASH_CTRL_MP_REGION_CFG2_OFFSET);
+ addr_hit[ 8] = (reg_addr == FLASH_CTRL_MP_REGION_CFG3_OFFSET);
+ addr_hit[ 9] = (reg_addr == FLASH_CTRL_MP_REGION_CFG4_OFFSET);
addr_hit[10] = (reg_addr == FLASH_CTRL_MP_REGION_CFG5_OFFSET);
addr_hit[11] = (reg_addr == FLASH_CTRL_MP_REGION_CFG6_OFFSET);
addr_hit[12] = (reg_addr == FLASH_CTRL_MP_REGION_CFG7_OFFSET);
@@ -2638,243 +2629,265 @@
end
end
- // Write Enable signal
+ // Check sub-word write is permitted
+ always_comb begin
+ wr_err = 1'b0;
+ if (addr_hit[ 0] && reg_we && (FLASH_CTRL_PERMIT[ 0] != (FLASH_CTRL_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 1] && reg_we && (FLASH_CTRL_PERMIT[ 1] != (FLASH_CTRL_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 2] && reg_we && (FLASH_CTRL_PERMIT[ 2] != (FLASH_CTRL_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 3] && reg_we && (FLASH_CTRL_PERMIT[ 3] != (FLASH_CTRL_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 4] && reg_we && (FLASH_CTRL_PERMIT[ 4] != (FLASH_CTRL_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 5] && reg_we && (FLASH_CTRL_PERMIT[ 5] != (FLASH_CTRL_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 6] && reg_we && (FLASH_CTRL_PERMIT[ 6] != (FLASH_CTRL_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 7] && reg_we && (FLASH_CTRL_PERMIT[ 7] != (FLASH_CTRL_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 8] && reg_we && (FLASH_CTRL_PERMIT[ 8] != (FLASH_CTRL_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 9] && reg_we && (FLASH_CTRL_PERMIT[ 9] != (FLASH_CTRL_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[10] && reg_we && (FLASH_CTRL_PERMIT[10] != (FLASH_CTRL_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[11] && reg_we && (FLASH_CTRL_PERMIT[11] != (FLASH_CTRL_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[12] && reg_we && (FLASH_CTRL_PERMIT[12] != (FLASH_CTRL_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[13] && reg_we && (FLASH_CTRL_PERMIT[13] != (FLASH_CTRL_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[14] && reg_we && (FLASH_CTRL_PERMIT[14] != (FLASH_CTRL_PERMIT[14] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[15] && reg_we && (FLASH_CTRL_PERMIT[15] != (FLASH_CTRL_PERMIT[15] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[16] && reg_we && (FLASH_CTRL_PERMIT[16] != (FLASH_CTRL_PERMIT[16] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[17] && reg_we && (FLASH_CTRL_PERMIT[17] != (FLASH_CTRL_PERMIT[17] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[18] && reg_we && (FLASH_CTRL_PERMIT[18] != (FLASH_CTRL_PERMIT[18] & reg_be))) wr_err = 1'b1 ;
+ end
- assign intr_state_prog_empty_we = addr_hit[0] && reg_we;
+ assign intr_state_prog_empty_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_prog_empty_wd = reg_wdata[0];
- assign intr_state_prog_lvl_we = addr_hit[0] && reg_we;
+ assign intr_state_prog_lvl_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_prog_lvl_wd = reg_wdata[1];
- assign intr_state_rd_full_we = addr_hit[0] && reg_we;
+ assign intr_state_rd_full_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_rd_full_wd = reg_wdata[2];
- assign intr_state_rd_lvl_we = addr_hit[0] && reg_we;
+ assign intr_state_rd_lvl_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_rd_lvl_wd = reg_wdata[3];
- assign intr_state_op_done_we = addr_hit[0] && reg_we;
+ assign intr_state_op_done_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_op_done_wd = reg_wdata[4];
- assign intr_state_op_error_we = addr_hit[0] && reg_we;
+ assign intr_state_op_error_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_op_error_wd = reg_wdata[5];
- assign intr_enable_prog_empty_we = addr_hit[1] && reg_we;
+ assign intr_enable_prog_empty_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_prog_empty_wd = reg_wdata[0];
- assign intr_enable_prog_lvl_we = addr_hit[1] && reg_we;
+ assign intr_enable_prog_lvl_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_prog_lvl_wd = reg_wdata[1];
- assign intr_enable_rd_full_we = addr_hit[1] && reg_we;
+ assign intr_enable_rd_full_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_rd_full_wd = reg_wdata[2];
- assign intr_enable_rd_lvl_we = addr_hit[1] && reg_we;
+ assign intr_enable_rd_lvl_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_rd_lvl_wd = reg_wdata[3];
- assign intr_enable_op_done_we = addr_hit[1] && reg_we;
+ assign intr_enable_op_done_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_op_done_wd = reg_wdata[4];
- assign intr_enable_op_error_we = addr_hit[1] && reg_we;
+ assign intr_enable_op_error_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_op_error_wd = reg_wdata[5];
- assign intr_test_prog_empty_we = addr_hit[2] && reg_we;
+ assign intr_test_prog_empty_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_prog_empty_wd = reg_wdata[0];
- assign intr_test_prog_lvl_we = addr_hit[2] && reg_we;
+ assign intr_test_prog_lvl_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_prog_lvl_wd = reg_wdata[1];
- assign intr_test_rd_full_we = addr_hit[2] && reg_we;
+ assign intr_test_rd_full_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_rd_full_wd = reg_wdata[2];
- assign intr_test_rd_lvl_we = addr_hit[2] && reg_we;
+ assign intr_test_rd_lvl_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_rd_lvl_wd = reg_wdata[3];
- assign intr_test_op_done_we = addr_hit[2] && reg_we;
+ assign intr_test_op_done_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_op_done_wd = reg_wdata[4];
- assign intr_test_op_error_we = addr_hit[2] && reg_we;
+ assign intr_test_op_error_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_op_error_wd = reg_wdata[5];
- assign control_start_we = addr_hit[3] && reg_we;
+ assign control_start_we = addr_hit[3] & reg_we & ~wr_err;
assign control_start_wd = reg_wdata[0];
- assign control_op_we = addr_hit[3] && reg_we;
+ assign control_op_we = addr_hit[3] & reg_we & ~wr_err;
assign control_op_wd = reg_wdata[5:4];
- assign control_erase_sel_we = addr_hit[3] && reg_we;
+ assign control_erase_sel_we = addr_hit[3] & reg_we & ~wr_err;
assign control_erase_sel_wd = reg_wdata[6];
- assign control_fifo_rst_we = addr_hit[3] && reg_we;
+ assign control_fifo_rst_we = addr_hit[3] & reg_we & ~wr_err;
assign control_fifo_rst_wd = reg_wdata[7];
- assign control_num_we = addr_hit[3] && reg_we;
+ assign control_num_we = addr_hit[3] & reg_we & ~wr_err;
assign control_num_wd = reg_wdata[27:16];
- assign addr_we = addr_hit[4] && reg_we;
+ assign addr_we = addr_hit[4] & reg_we & ~wr_err;
assign addr_wd = reg_wdata[31:0];
- assign mp_region_cfg0_en0_we = addr_hit[5] && reg_we;
+ assign mp_region_cfg0_en0_we = addr_hit[5] & reg_we & ~wr_err;
assign mp_region_cfg0_en0_wd = reg_wdata[0];
- assign mp_region_cfg0_rd_en0_we = addr_hit[5] && reg_we;
+ assign mp_region_cfg0_rd_en0_we = addr_hit[5] & reg_we & ~wr_err;
assign mp_region_cfg0_rd_en0_wd = reg_wdata[1];
- assign mp_region_cfg0_prog_en0_we = addr_hit[5] && reg_we;
+ assign mp_region_cfg0_prog_en0_we = addr_hit[5] & reg_we & ~wr_err;
assign mp_region_cfg0_prog_en0_wd = reg_wdata[2];
- assign mp_region_cfg0_erase_en0_we = addr_hit[5] && reg_we;
+ assign mp_region_cfg0_erase_en0_we = addr_hit[5] & reg_we & ~wr_err;
assign mp_region_cfg0_erase_en0_wd = reg_wdata[3];
- assign mp_region_cfg0_base0_we = addr_hit[5] && reg_we;
+ assign mp_region_cfg0_base0_we = addr_hit[5] & reg_we & ~wr_err;
assign mp_region_cfg0_base0_wd = reg_wdata[12:4];
- assign mp_region_cfg0_size0_we = addr_hit[5] && reg_we;
+ assign mp_region_cfg0_size0_we = addr_hit[5] & reg_we & ~wr_err;
assign mp_region_cfg0_size0_wd = reg_wdata[24:16];
- assign mp_region_cfg1_en1_we = addr_hit[6] && reg_we;
+ assign mp_region_cfg1_en1_we = addr_hit[6] & reg_we & ~wr_err;
assign mp_region_cfg1_en1_wd = reg_wdata[0];
- assign mp_region_cfg1_rd_en1_we = addr_hit[6] && reg_we;
+ assign mp_region_cfg1_rd_en1_we = addr_hit[6] & reg_we & ~wr_err;
assign mp_region_cfg1_rd_en1_wd = reg_wdata[1];
- assign mp_region_cfg1_prog_en1_we = addr_hit[6] && reg_we;
+ assign mp_region_cfg1_prog_en1_we = addr_hit[6] & reg_we & ~wr_err;
assign mp_region_cfg1_prog_en1_wd = reg_wdata[2];
- assign mp_region_cfg1_erase_en1_we = addr_hit[6] && reg_we;
+ assign mp_region_cfg1_erase_en1_we = addr_hit[6] & reg_we & ~wr_err;
assign mp_region_cfg1_erase_en1_wd = reg_wdata[3];
- assign mp_region_cfg1_base1_we = addr_hit[6] && reg_we;
+ assign mp_region_cfg1_base1_we = addr_hit[6] & reg_we & ~wr_err;
assign mp_region_cfg1_base1_wd = reg_wdata[12:4];
- assign mp_region_cfg1_size1_we = addr_hit[6] && reg_we;
+ assign mp_region_cfg1_size1_we = addr_hit[6] & reg_we & ~wr_err;
assign mp_region_cfg1_size1_wd = reg_wdata[24:16];
- assign mp_region_cfg2_en2_we = addr_hit[7] && reg_we;
+ assign mp_region_cfg2_en2_we = addr_hit[7] & reg_we & ~wr_err;
assign mp_region_cfg2_en2_wd = reg_wdata[0];
- assign mp_region_cfg2_rd_en2_we = addr_hit[7] && reg_we;
+ assign mp_region_cfg2_rd_en2_we = addr_hit[7] & reg_we & ~wr_err;
assign mp_region_cfg2_rd_en2_wd = reg_wdata[1];
- assign mp_region_cfg2_prog_en2_we = addr_hit[7] && reg_we;
+ assign mp_region_cfg2_prog_en2_we = addr_hit[7] & reg_we & ~wr_err;
assign mp_region_cfg2_prog_en2_wd = reg_wdata[2];
- assign mp_region_cfg2_erase_en2_we = addr_hit[7] && reg_we;
+ assign mp_region_cfg2_erase_en2_we = addr_hit[7] & reg_we & ~wr_err;
assign mp_region_cfg2_erase_en2_wd = reg_wdata[3];
- assign mp_region_cfg2_base2_we = addr_hit[7] && reg_we;
+ assign mp_region_cfg2_base2_we = addr_hit[7] & reg_we & ~wr_err;
assign mp_region_cfg2_base2_wd = reg_wdata[12:4];
- assign mp_region_cfg2_size2_we = addr_hit[7] && reg_we;
+ assign mp_region_cfg2_size2_we = addr_hit[7] & reg_we & ~wr_err;
assign mp_region_cfg2_size2_wd = reg_wdata[24:16];
- assign mp_region_cfg3_en3_we = addr_hit[8] && reg_we;
+ assign mp_region_cfg3_en3_we = addr_hit[8] & reg_we & ~wr_err;
assign mp_region_cfg3_en3_wd = reg_wdata[0];
- assign mp_region_cfg3_rd_en3_we = addr_hit[8] && reg_we;
+ assign mp_region_cfg3_rd_en3_we = addr_hit[8] & reg_we & ~wr_err;
assign mp_region_cfg3_rd_en3_wd = reg_wdata[1];
- assign mp_region_cfg3_prog_en3_we = addr_hit[8] && reg_we;
+ assign mp_region_cfg3_prog_en3_we = addr_hit[8] & reg_we & ~wr_err;
assign mp_region_cfg3_prog_en3_wd = reg_wdata[2];
- assign mp_region_cfg3_erase_en3_we = addr_hit[8] && reg_we;
+ assign mp_region_cfg3_erase_en3_we = addr_hit[8] & reg_we & ~wr_err;
assign mp_region_cfg3_erase_en3_wd = reg_wdata[3];
- assign mp_region_cfg3_base3_we = addr_hit[8] && reg_we;
+ assign mp_region_cfg3_base3_we = addr_hit[8] & reg_we & ~wr_err;
assign mp_region_cfg3_base3_wd = reg_wdata[12:4];
- assign mp_region_cfg3_size3_we = addr_hit[8] && reg_we;
+ assign mp_region_cfg3_size3_we = addr_hit[8] & reg_we & ~wr_err;
assign mp_region_cfg3_size3_wd = reg_wdata[24:16];
- assign mp_region_cfg4_en4_we = addr_hit[9] && reg_we;
+ assign mp_region_cfg4_en4_we = addr_hit[9] & reg_we & ~wr_err;
assign mp_region_cfg4_en4_wd = reg_wdata[0];
- assign mp_region_cfg4_rd_en4_we = addr_hit[9] && reg_we;
+ assign mp_region_cfg4_rd_en4_we = addr_hit[9] & reg_we & ~wr_err;
assign mp_region_cfg4_rd_en4_wd = reg_wdata[1];
- assign mp_region_cfg4_prog_en4_we = addr_hit[9] && reg_we;
+ assign mp_region_cfg4_prog_en4_we = addr_hit[9] & reg_we & ~wr_err;
assign mp_region_cfg4_prog_en4_wd = reg_wdata[2];
- assign mp_region_cfg4_erase_en4_we = addr_hit[9] && reg_we;
+ assign mp_region_cfg4_erase_en4_we = addr_hit[9] & reg_we & ~wr_err;
assign mp_region_cfg4_erase_en4_wd = reg_wdata[3];
- assign mp_region_cfg4_base4_we = addr_hit[9] && reg_we;
+ assign mp_region_cfg4_base4_we = addr_hit[9] & reg_we & ~wr_err;
assign mp_region_cfg4_base4_wd = reg_wdata[12:4];
- assign mp_region_cfg4_size4_we = addr_hit[9] && reg_we;
+ assign mp_region_cfg4_size4_we = addr_hit[9] & reg_we & ~wr_err;
assign mp_region_cfg4_size4_wd = reg_wdata[24:16];
- assign mp_region_cfg5_en5_we = addr_hit[10] && reg_we;
+ assign mp_region_cfg5_en5_we = addr_hit[10] & reg_we & ~wr_err;
assign mp_region_cfg5_en5_wd = reg_wdata[0];
- assign mp_region_cfg5_rd_en5_we = addr_hit[10] && reg_we;
+ assign mp_region_cfg5_rd_en5_we = addr_hit[10] & reg_we & ~wr_err;
assign mp_region_cfg5_rd_en5_wd = reg_wdata[1];
- assign mp_region_cfg5_prog_en5_we = addr_hit[10] && reg_we;
+ assign mp_region_cfg5_prog_en5_we = addr_hit[10] & reg_we & ~wr_err;
assign mp_region_cfg5_prog_en5_wd = reg_wdata[2];
- assign mp_region_cfg5_erase_en5_we = addr_hit[10] && reg_we;
+ assign mp_region_cfg5_erase_en5_we = addr_hit[10] & reg_we & ~wr_err;
assign mp_region_cfg5_erase_en5_wd = reg_wdata[3];
- assign mp_region_cfg5_base5_we = addr_hit[10] && reg_we;
+ assign mp_region_cfg5_base5_we = addr_hit[10] & reg_we & ~wr_err;
assign mp_region_cfg5_base5_wd = reg_wdata[12:4];
- assign mp_region_cfg5_size5_we = addr_hit[10] && reg_we;
+ assign mp_region_cfg5_size5_we = addr_hit[10] & reg_we & ~wr_err;
assign mp_region_cfg5_size5_wd = reg_wdata[24:16];
- assign mp_region_cfg6_en6_we = addr_hit[11] && reg_we;
+ assign mp_region_cfg6_en6_we = addr_hit[11] & reg_we & ~wr_err;
assign mp_region_cfg6_en6_wd = reg_wdata[0];
- assign mp_region_cfg6_rd_en6_we = addr_hit[11] && reg_we;
+ assign mp_region_cfg6_rd_en6_we = addr_hit[11] & reg_we & ~wr_err;
assign mp_region_cfg6_rd_en6_wd = reg_wdata[1];
- assign mp_region_cfg6_prog_en6_we = addr_hit[11] && reg_we;
+ assign mp_region_cfg6_prog_en6_we = addr_hit[11] & reg_we & ~wr_err;
assign mp_region_cfg6_prog_en6_wd = reg_wdata[2];
- assign mp_region_cfg6_erase_en6_we = addr_hit[11] && reg_we;
+ assign mp_region_cfg6_erase_en6_we = addr_hit[11] & reg_we & ~wr_err;
assign mp_region_cfg6_erase_en6_wd = reg_wdata[3];
- assign mp_region_cfg6_base6_we = addr_hit[11] && reg_we;
+ assign mp_region_cfg6_base6_we = addr_hit[11] & reg_we & ~wr_err;
assign mp_region_cfg6_base6_wd = reg_wdata[12:4];
- assign mp_region_cfg6_size6_we = addr_hit[11] && reg_we;
+ assign mp_region_cfg6_size6_we = addr_hit[11] & reg_we & ~wr_err;
assign mp_region_cfg6_size6_wd = reg_wdata[24:16];
- assign mp_region_cfg7_en7_we = addr_hit[12] && reg_we;
+ assign mp_region_cfg7_en7_we = addr_hit[12] & reg_we & ~wr_err;
assign mp_region_cfg7_en7_wd = reg_wdata[0];
- assign mp_region_cfg7_rd_en7_we = addr_hit[12] && reg_we;
+ assign mp_region_cfg7_rd_en7_we = addr_hit[12] & reg_we & ~wr_err;
assign mp_region_cfg7_rd_en7_wd = reg_wdata[1];
- assign mp_region_cfg7_prog_en7_we = addr_hit[12] && reg_we;
+ assign mp_region_cfg7_prog_en7_we = addr_hit[12] & reg_we & ~wr_err;
assign mp_region_cfg7_prog_en7_wd = reg_wdata[2];
- assign mp_region_cfg7_erase_en7_we = addr_hit[12] && reg_we;
+ assign mp_region_cfg7_erase_en7_we = addr_hit[12] & reg_we & ~wr_err;
assign mp_region_cfg7_erase_en7_wd = reg_wdata[3];
- assign mp_region_cfg7_base7_we = addr_hit[12] && reg_we;
+ assign mp_region_cfg7_base7_we = addr_hit[12] & reg_we & ~wr_err;
assign mp_region_cfg7_base7_wd = reg_wdata[12:4];
- assign mp_region_cfg7_size7_we = addr_hit[12] && reg_we;
+ assign mp_region_cfg7_size7_we = addr_hit[12] & reg_we & ~wr_err;
assign mp_region_cfg7_size7_wd = reg_wdata[24:16];
- assign default_region_rd_en_we = addr_hit[13] && reg_we;
+ assign default_region_rd_en_we = addr_hit[13] & reg_we & ~wr_err;
assign default_region_rd_en_wd = reg_wdata[0];
- assign default_region_prog_en_we = addr_hit[13] && reg_we;
+ assign default_region_prog_en_we = addr_hit[13] & reg_we & ~wr_err;
assign default_region_prog_en_wd = reg_wdata[1];
- assign default_region_erase_en_we = addr_hit[13] && reg_we;
+ assign default_region_erase_en_we = addr_hit[13] & reg_we & ~wr_err;
assign default_region_erase_en_wd = reg_wdata[2];
- assign mp_bank_cfg_erase_en0_we = addr_hit[14] && reg_we;
+ assign mp_bank_cfg_erase_en0_we = addr_hit[14] & reg_we & ~wr_err;
assign mp_bank_cfg_erase_en0_wd = reg_wdata[1];
- assign mp_bank_cfg_erase_en1_we = addr_hit[14] && reg_we;
+ assign mp_bank_cfg_erase_en1_we = addr_hit[14] & reg_we & ~wr_err;
assign mp_bank_cfg_erase_en1_wd = reg_wdata[2];
- assign op_status_done_we = addr_hit[15] && reg_we;
+ assign op_status_done_we = addr_hit[15] & reg_we & ~wr_err;
assign op_status_done_wd = reg_wdata[0];
- assign op_status_err_we = addr_hit[15] && reg_we;
+ assign op_status_err_we = addr_hit[15] & reg_we & ~wr_err;
assign op_status_err_wd = reg_wdata[1];
assign status_rd_full_re = addr_hit[16] && reg_re;
@@ -2891,13 +2904,13 @@
assign status_error_bank_re = addr_hit[16] && reg_re;
- assign scratch_we = addr_hit[17] && reg_we;
+ assign scratch_we = addr_hit[17] & reg_we & ~wr_err;
assign scratch_wd = reg_wdata[31:0];
- assign fifo_lvl_prog_we = addr_hit[18] && reg_we;
+ assign fifo_lvl_prog_we = addr_hit[18] & reg_we & ~wr_err;
assign fifo_lvl_prog_wd = reg_wdata[4:0];
- assign fifo_lvl_rd_we = addr_hit[18] && reg_we;
+ assign fifo_lvl_rd_we = addr_hit[18] & reg_we & ~wr_err;
assign fifo_lvl_rd_wd = reg_wdata[12:8];
// Read data return
diff --git a/hw/ip/gpio/rtl/gpio_reg_pkg.sv b/hw/ip/gpio/rtl/gpio_reg_pkg.sv
index 0f368a4..fa65774 100644
--- a/hw/ip/gpio/rtl/gpio_reg_pkg.sv
+++ b/hw/ip/gpio/rtl/gpio_reg_pkg.sv
@@ -153,4 +153,42 @@
parameter GPIO_CTRL_EN_INPUT_FILTER_OFFSET = 6'h 38;
+ // Register Index
+ typedef enum int {
+ GPIO_INTR_STATE,
+ GPIO_INTR_ENABLE,
+ GPIO_INTR_TEST,
+ GPIO_DATA_IN,
+ GPIO_DIRECT_OUT,
+ GPIO_MASKED_OUT_LOWER,
+ GPIO_MASKED_OUT_UPPER,
+ GPIO_DIRECT_OE,
+ GPIO_MASKED_OE_LOWER,
+ GPIO_MASKED_OE_UPPER,
+ GPIO_INTR_CTRL_EN_RISING,
+ GPIO_INTR_CTRL_EN_FALLING,
+ GPIO_INTR_CTRL_EN_LVLHIGH,
+ GPIO_INTR_CTRL_EN_LVLLOW,
+ GPIO_CTRL_EN_INPUT_FILTER
+ } gpio_id_e;
+
+ // Register width information to check illegal writes
+ localparam logic [3:0] GPIO_PERMIT [15] = '{
+ 4'b 1111, // index[ 0] GPIO_INTR_STATE
+ 4'b 1111, // index[ 1] GPIO_INTR_ENABLE
+ 4'b 1111, // index[ 2] GPIO_INTR_TEST
+ 4'b 1111, // index[ 3] GPIO_DATA_IN
+ 4'b 1111, // index[ 4] GPIO_DIRECT_OUT
+ 4'b 1111, // index[ 5] GPIO_MASKED_OUT_LOWER
+ 4'b 1111, // index[ 6] GPIO_MASKED_OUT_UPPER
+ 4'b 1111, // index[ 7] GPIO_DIRECT_OE
+ 4'b 1111, // index[ 8] GPIO_MASKED_OE_LOWER
+ 4'b 1111, // index[ 9] GPIO_MASKED_OE_UPPER
+ 4'b 1111, // index[10] GPIO_INTR_CTRL_EN_RISING
+ 4'b 1111, // index[11] GPIO_INTR_CTRL_EN_FALLING
+ 4'b 1111, // index[12] GPIO_INTR_CTRL_EN_LVLHIGH
+ 4'b 1111, // index[13] GPIO_INTR_CTRL_EN_LVLLOW
+ 4'b 1111, // index[14] GPIO_CTRL_EN_INPUT_FILTER
+ };
endpackage
+
diff --git a/hw/ip/gpio/rtl/gpio_reg_top.sv b/hw/ip/gpio/rtl/gpio_reg_top.sv
index 0a0e54f..ac1c48f 100644
--- a/hw/ip/gpio/rtl/gpio_reg_top.sv
+++ b/hw/ip/gpio/rtl/gpio_reg_top.sv
@@ -32,7 +32,7 @@
logic [DW-1:0] reg_rdata;
logic reg_error;
- logic malformed, addrmiss;
+ logic addrmiss, wr_err;
logic [DW-1:0] reg_rdata_next;
@@ -62,16 +62,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = malformed | addrmiss ;
-
- // Malformed request check only affects to the write access
- always_comb begin : malformed_check
- if (reg_we && (reg_be != '1)) begin
- malformed = 1'b1;
- end else begin
- malformed = 1'b0;
- end
- end
+ assign reg_error = addrmiss | wr_err;
// TODO(eunchan): Revise Register Interface logic after REG INTF finalized
// TODO(eunchan): Make concrete scenario
@@ -549,16 +540,16 @@
logic [14:0] addr_hit;
always_comb begin
addr_hit = '0;
- addr_hit[0] = (reg_addr == GPIO_INTR_STATE_OFFSET);
- addr_hit[1] = (reg_addr == GPIO_INTR_ENABLE_OFFSET);
- addr_hit[2] = (reg_addr == GPIO_INTR_TEST_OFFSET);
- addr_hit[3] = (reg_addr == GPIO_DATA_IN_OFFSET);
- addr_hit[4] = (reg_addr == GPIO_DIRECT_OUT_OFFSET);
- addr_hit[5] = (reg_addr == GPIO_MASKED_OUT_LOWER_OFFSET);
- addr_hit[6] = (reg_addr == GPIO_MASKED_OUT_UPPER_OFFSET);
- addr_hit[7] = (reg_addr == GPIO_DIRECT_OE_OFFSET);
- addr_hit[8] = (reg_addr == GPIO_MASKED_OE_LOWER_OFFSET);
- addr_hit[9] = (reg_addr == GPIO_MASKED_OE_UPPER_OFFSET);
+ addr_hit[ 0] = (reg_addr == GPIO_INTR_STATE_OFFSET);
+ addr_hit[ 1] = (reg_addr == GPIO_INTR_ENABLE_OFFSET);
+ addr_hit[ 2] = (reg_addr == GPIO_INTR_TEST_OFFSET);
+ addr_hit[ 3] = (reg_addr == GPIO_DATA_IN_OFFSET);
+ addr_hit[ 4] = (reg_addr == GPIO_DIRECT_OUT_OFFSET);
+ addr_hit[ 5] = (reg_addr == GPIO_MASKED_OUT_LOWER_OFFSET);
+ addr_hit[ 6] = (reg_addr == GPIO_MASKED_OUT_UPPER_OFFSET);
+ addr_hit[ 7] = (reg_addr == GPIO_DIRECT_OE_OFFSET);
+ addr_hit[ 8] = (reg_addr == GPIO_MASKED_OE_LOWER_OFFSET);
+ addr_hit[ 9] = (reg_addr == GPIO_MASKED_OE_UPPER_OFFSET);
addr_hit[10] = (reg_addr == GPIO_INTR_CTRL_EN_RISING_OFFSET);
addr_hit[11] = (reg_addr == GPIO_INTR_CTRL_EN_FALLING_OFFSET);
addr_hit[12] = (reg_addr == GPIO_INTR_CTRL_EN_LVLHIGH_OFFSET);
@@ -574,69 +565,87 @@
end
end
- // Write Enable signal
+ // Check sub-word write is permitted
+ always_comb begin
+ wr_err = 1'b0;
+ if (addr_hit[ 0] && reg_we && (GPIO_PERMIT[ 0] != (GPIO_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 1] && reg_we && (GPIO_PERMIT[ 1] != (GPIO_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 2] && reg_we && (GPIO_PERMIT[ 2] != (GPIO_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 3] && reg_we && (GPIO_PERMIT[ 3] != (GPIO_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 4] && reg_we && (GPIO_PERMIT[ 4] != (GPIO_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 5] && reg_we && (GPIO_PERMIT[ 5] != (GPIO_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 6] && reg_we && (GPIO_PERMIT[ 6] != (GPIO_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 7] && reg_we && (GPIO_PERMIT[ 7] != (GPIO_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 8] && reg_we && (GPIO_PERMIT[ 8] != (GPIO_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 9] && reg_we && (GPIO_PERMIT[ 9] != (GPIO_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[10] && reg_we && (GPIO_PERMIT[10] != (GPIO_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[11] && reg_we && (GPIO_PERMIT[11] != (GPIO_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[12] && reg_we && (GPIO_PERMIT[12] != (GPIO_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[13] && reg_we && (GPIO_PERMIT[13] != (GPIO_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[14] && reg_we && (GPIO_PERMIT[14] != (GPIO_PERMIT[14] & reg_be))) wr_err = 1'b1 ;
+ end
- assign intr_state_we = addr_hit[0] && reg_we;
+ assign intr_state_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_wd = reg_wdata[31:0];
- assign intr_enable_we = addr_hit[1] && reg_we;
+ assign intr_enable_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_wd = reg_wdata[31:0];
- assign intr_test_we = addr_hit[2] && reg_we;
+ assign intr_test_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_wd = reg_wdata[31:0];
- assign direct_out_we = addr_hit[4] && reg_we;
+ assign direct_out_we = addr_hit[4] & reg_we & ~wr_err;
assign direct_out_wd = reg_wdata[31:0];
assign direct_out_re = addr_hit[4] && reg_re;
- assign masked_out_lower_data_we = addr_hit[5] && reg_we;
+ assign masked_out_lower_data_we = addr_hit[5] & reg_we & ~wr_err;
assign masked_out_lower_data_wd = reg_wdata[15:0];
assign masked_out_lower_data_re = addr_hit[5] && reg_re;
- assign masked_out_lower_mask_we = addr_hit[5] && reg_we;
+ assign masked_out_lower_mask_we = addr_hit[5] & reg_we & ~wr_err;
assign masked_out_lower_mask_wd = reg_wdata[31:16];
- assign masked_out_upper_data_we = addr_hit[6] && reg_we;
+ assign masked_out_upper_data_we = addr_hit[6] & reg_we & ~wr_err;
assign masked_out_upper_data_wd = reg_wdata[15:0];
assign masked_out_upper_data_re = addr_hit[6] && reg_re;
- assign masked_out_upper_mask_we = addr_hit[6] && reg_we;
+ assign masked_out_upper_mask_we = addr_hit[6] & reg_we & ~wr_err;
assign masked_out_upper_mask_wd = reg_wdata[31:16];
- assign direct_oe_we = addr_hit[7] && reg_we;
+ assign direct_oe_we = addr_hit[7] & reg_we & ~wr_err;
assign direct_oe_wd = reg_wdata[31:0];
assign direct_oe_re = addr_hit[7] && reg_re;
- assign masked_oe_lower_data_we = addr_hit[8] && reg_we;
+ assign masked_oe_lower_data_we = addr_hit[8] & reg_we & ~wr_err;
assign masked_oe_lower_data_wd = reg_wdata[15:0];
assign masked_oe_lower_data_re = addr_hit[8] && reg_re;
- assign masked_oe_lower_mask_we = addr_hit[8] && reg_we;
+ assign masked_oe_lower_mask_we = addr_hit[8] & reg_we & ~wr_err;
assign masked_oe_lower_mask_wd = reg_wdata[31:16];
assign masked_oe_lower_mask_re = addr_hit[8] && reg_re;
- assign masked_oe_upper_data_we = addr_hit[9] && reg_we;
+ assign masked_oe_upper_data_we = addr_hit[9] & reg_we & ~wr_err;
assign masked_oe_upper_data_wd = reg_wdata[15:0];
assign masked_oe_upper_data_re = addr_hit[9] && reg_re;
- assign masked_oe_upper_mask_we = addr_hit[9] && reg_we;
+ assign masked_oe_upper_mask_we = addr_hit[9] & reg_we & ~wr_err;
assign masked_oe_upper_mask_wd = reg_wdata[31:16];
assign masked_oe_upper_mask_re = addr_hit[9] && reg_re;
- assign intr_ctrl_en_rising_we = addr_hit[10] && reg_we;
+ assign intr_ctrl_en_rising_we = addr_hit[10] & reg_we & ~wr_err;
assign intr_ctrl_en_rising_wd = reg_wdata[31:0];
- assign intr_ctrl_en_falling_we = addr_hit[11] && reg_we;
+ assign intr_ctrl_en_falling_we = addr_hit[11] & reg_we & ~wr_err;
assign intr_ctrl_en_falling_wd = reg_wdata[31:0];
- assign intr_ctrl_en_lvlhigh_we = addr_hit[12] && reg_we;
+ assign intr_ctrl_en_lvlhigh_we = addr_hit[12] & reg_we & ~wr_err;
assign intr_ctrl_en_lvlhigh_wd = reg_wdata[31:0];
- assign intr_ctrl_en_lvllow_we = addr_hit[13] && reg_we;
+ assign intr_ctrl_en_lvllow_we = addr_hit[13] & reg_we & ~wr_err;
assign intr_ctrl_en_lvllow_wd = reg_wdata[31:0];
- assign ctrl_en_input_filter_we = addr_hit[14] && reg_we;
+ assign ctrl_en_input_filter_we = addr_hit[14] & reg_we & ~wr_err;
assign ctrl_en_input_filter_wd = reg_wdata[31:0];
// Read data return
diff --git a/hw/ip/hmac/rtl/hmac_reg_pkg.sv b/hw/ip/hmac/rtl/hmac_reg_pkg.sv
index d984fac..7552769 100644
--- a/hw/ip/hmac/rtl/hmac_reg_pkg.sv
+++ b/hw/ip/hmac/rtl/hmac_reg_pkg.sv
@@ -210,4 +210,62 @@
parameter HMAC_MSG_FIFO_OFFSET = 12'h 800;
parameter HMAC_MSG_FIFO_SIZE = 12'h 800;
+ // Register Index
+ typedef enum int {
+ HMAC_INTR_STATE,
+ HMAC_INTR_ENABLE,
+ HMAC_INTR_TEST,
+ HMAC_CFG,
+ HMAC_CMD,
+ HMAC_STATUS,
+ HMAC_WIPE_SECRET,
+ HMAC_KEY0,
+ HMAC_KEY1,
+ HMAC_KEY2,
+ HMAC_KEY3,
+ HMAC_KEY4,
+ HMAC_KEY5,
+ HMAC_KEY6,
+ HMAC_KEY7,
+ HMAC_DIGEST0,
+ HMAC_DIGEST1,
+ HMAC_DIGEST2,
+ HMAC_DIGEST3,
+ HMAC_DIGEST4,
+ HMAC_DIGEST5,
+ HMAC_DIGEST6,
+ HMAC_DIGEST7,
+ HMAC_MSG_LENGTH_LOWER,
+ HMAC_MSG_LENGTH_UPPER
+ } hmac_id_e;
+
+ // Register width information to check illegal writes
+ localparam logic [3:0] HMAC_PERMIT [25] = '{
+ 4'b 0001, // index[ 0] HMAC_INTR_STATE
+ 4'b 0001, // index[ 1] HMAC_INTR_ENABLE
+ 4'b 0001, // index[ 2] HMAC_INTR_TEST
+ 4'b 0001, // index[ 3] HMAC_CFG
+ 4'b 0001, // index[ 4] HMAC_CMD
+ 4'b 0011, // index[ 5] HMAC_STATUS
+ 4'b 1111, // index[ 6] HMAC_WIPE_SECRET
+ 4'b 1111, // index[ 7] HMAC_KEY0
+ 4'b 1111, // index[ 8] HMAC_KEY1
+ 4'b 1111, // index[ 9] HMAC_KEY2
+ 4'b 1111, // index[10] HMAC_KEY3
+ 4'b 1111, // index[11] HMAC_KEY4
+ 4'b 1111, // index[12] HMAC_KEY5
+ 4'b 1111, // index[13] HMAC_KEY6
+ 4'b 1111, // index[14] HMAC_KEY7
+ 4'b 1111, // index[15] HMAC_DIGEST0
+ 4'b 1111, // index[16] HMAC_DIGEST1
+ 4'b 1111, // index[17] HMAC_DIGEST2
+ 4'b 1111, // index[18] HMAC_DIGEST3
+ 4'b 1111, // index[19] HMAC_DIGEST4
+ 4'b 1111, // index[20] HMAC_DIGEST5
+ 4'b 1111, // index[21] HMAC_DIGEST6
+ 4'b 1111, // index[22] HMAC_DIGEST7
+ 4'b 1111, // index[23] HMAC_MSG_LENGTH_LOWER
+ 4'b 1111, // index[24] HMAC_MSG_LENGTH_UPPER
+ };
endpackage
+
diff --git a/hw/ip/hmac/rtl/hmac_reg_top.sv b/hw/ip/hmac/rtl/hmac_reg_top.sv
index 18af9cc..aceedea 100644
--- a/hw/ip/hmac/rtl/hmac_reg_top.sv
+++ b/hw/ip/hmac/rtl/hmac_reg_top.sv
@@ -37,7 +37,7 @@
logic [DW-1:0] reg_rdata;
logic reg_error;
- logic malformed, addrmiss;
+ logic addrmiss, wr_err;
logic [DW-1:0] reg_rdata_next;
@@ -108,16 +108,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = malformed | addrmiss ;
-
- // Malformed request check only affects to the write access
- always_comb begin : malformed_check
- if (reg_we && (reg_be != '1)) begin
- malformed = 1'b1;
- end else begin
- malformed = 1'b0;
- end
- end
+ assign reg_error = addrmiss | wr_err;
// TODO(eunchan): Revise Register Interface logic after REG INTF finalized
// TODO(eunchan): Make concrete scenario
@@ -947,16 +938,16 @@
logic [24:0] addr_hit;
always_comb begin
addr_hit = '0;
- addr_hit[0] = (reg_addr == HMAC_INTR_STATE_OFFSET);
- addr_hit[1] = (reg_addr == HMAC_INTR_ENABLE_OFFSET);
- addr_hit[2] = (reg_addr == HMAC_INTR_TEST_OFFSET);
- addr_hit[3] = (reg_addr == HMAC_CFG_OFFSET);
- addr_hit[4] = (reg_addr == HMAC_CMD_OFFSET);
- addr_hit[5] = (reg_addr == HMAC_STATUS_OFFSET);
- addr_hit[6] = (reg_addr == HMAC_WIPE_SECRET_OFFSET);
- addr_hit[7] = (reg_addr == HMAC_KEY0_OFFSET);
- addr_hit[8] = (reg_addr == HMAC_KEY1_OFFSET);
- addr_hit[9] = (reg_addr == HMAC_KEY2_OFFSET);
+ addr_hit[ 0] = (reg_addr == HMAC_INTR_STATE_OFFSET);
+ addr_hit[ 1] = (reg_addr == HMAC_INTR_ENABLE_OFFSET);
+ addr_hit[ 2] = (reg_addr == HMAC_INTR_TEST_OFFSET);
+ addr_hit[ 3] = (reg_addr == HMAC_CFG_OFFSET);
+ addr_hit[ 4] = (reg_addr == HMAC_CMD_OFFSET);
+ addr_hit[ 5] = (reg_addr == HMAC_STATUS_OFFSET);
+ addr_hit[ 6] = (reg_addr == HMAC_WIPE_SECRET_OFFSET);
+ addr_hit[ 7] = (reg_addr == HMAC_KEY0_OFFSET);
+ addr_hit[ 8] = (reg_addr == HMAC_KEY1_OFFSET);
+ addr_hit[ 9] = (reg_addr == HMAC_KEY2_OFFSET);
addr_hit[10] = (reg_addr == HMAC_KEY3_OFFSET);
addr_hit[11] = (reg_addr == HMAC_KEY4_OFFSET);
addr_hit[12] = (reg_addr == HMAC_KEY5_OFFSET);
@@ -982,42 +973,70 @@
end
end
- // Write Enable signal
+ // Check sub-word write is permitted
+ always_comb begin
+ wr_err = 1'b0;
+ if (addr_hit[ 0] && reg_we && (HMAC_PERMIT[ 0] != (HMAC_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 1] && reg_we && (HMAC_PERMIT[ 1] != (HMAC_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 2] && reg_we && (HMAC_PERMIT[ 2] != (HMAC_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 3] && reg_we && (HMAC_PERMIT[ 3] != (HMAC_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 4] && reg_we && (HMAC_PERMIT[ 4] != (HMAC_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 5] && reg_we && (HMAC_PERMIT[ 5] != (HMAC_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 6] && reg_we && (HMAC_PERMIT[ 6] != (HMAC_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 7] && reg_we && (HMAC_PERMIT[ 7] != (HMAC_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 8] && reg_we && (HMAC_PERMIT[ 8] != (HMAC_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 9] && reg_we && (HMAC_PERMIT[ 9] != (HMAC_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[10] && reg_we && (HMAC_PERMIT[10] != (HMAC_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[11] && reg_we && (HMAC_PERMIT[11] != (HMAC_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[12] && reg_we && (HMAC_PERMIT[12] != (HMAC_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[13] && reg_we && (HMAC_PERMIT[13] != (HMAC_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[14] && reg_we && (HMAC_PERMIT[14] != (HMAC_PERMIT[14] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[15] && reg_we && (HMAC_PERMIT[15] != (HMAC_PERMIT[15] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[16] && reg_we && (HMAC_PERMIT[16] != (HMAC_PERMIT[16] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[17] && reg_we && (HMAC_PERMIT[17] != (HMAC_PERMIT[17] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[18] && reg_we && (HMAC_PERMIT[18] != (HMAC_PERMIT[18] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[19] && reg_we && (HMAC_PERMIT[19] != (HMAC_PERMIT[19] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[20] && reg_we && (HMAC_PERMIT[20] != (HMAC_PERMIT[20] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[21] && reg_we && (HMAC_PERMIT[21] != (HMAC_PERMIT[21] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[22] && reg_we && (HMAC_PERMIT[22] != (HMAC_PERMIT[22] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[23] && reg_we && (HMAC_PERMIT[23] != (HMAC_PERMIT[23] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[24] && reg_we && (HMAC_PERMIT[24] != (HMAC_PERMIT[24] & reg_be))) wr_err = 1'b1 ;
+ end
- assign intr_state_hmac_done_we = addr_hit[0] && reg_we;
+ assign intr_state_hmac_done_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_hmac_done_wd = reg_wdata[0];
- assign intr_state_fifo_full_we = addr_hit[0] && reg_we;
+ assign intr_state_fifo_full_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_fifo_full_wd = reg_wdata[1];
- assign intr_enable_hmac_done_we = addr_hit[1] && reg_we;
+ assign intr_enable_hmac_done_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_hmac_done_wd = reg_wdata[0];
- assign intr_enable_fifo_full_we = addr_hit[1] && reg_we;
+ assign intr_enable_fifo_full_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_fifo_full_wd = reg_wdata[1];
- assign intr_test_hmac_done_we = addr_hit[2] && reg_we;
+ assign intr_test_hmac_done_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_hmac_done_wd = reg_wdata[0];
- assign intr_test_fifo_full_we = addr_hit[2] && reg_we;
+ assign intr_test_fifo_full_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_fifo_full_wd = reg_wdata[1];
- assign cfg_hmac_en_we = addr_hit[3] && reg_we;
+ assign cfg_hmac_en_we = addr_hit[3] & reg_we & ~wr_err;
assign cfg_hmac_en_wd = reg_wdata[0];
- assign cfg_sha_en_we = addr_hit[3] && reg_we;
+ assign cfg_sha_en_we = addr_hit[3] & reg_we & ~wr_err;
assign cfg_sha_en_wd = reg_wdata[1];
- assign cfg_endian_swap_we = addr_hit[3] && reg_we;
+ assign cfg_endian_swap_we = addr_hit[3] & reg_we & ~wr_err;
assign cfg_endian_swap_wd = reg_wdata[2];
- assign cfg_digest_swap_we = addr_hit[3] && reg_we;
+ assign cfg_digest_swap_we = addr_hit[3] & reg_we & ~wr_err;
assign cfg_digest_swap_wd = reg_wdata[3];
- assign cmd_hash_start_we = addr_hit[4] && reg_we;
+ assign cmd_hash_start_we = addr_hit[4] & reg_we & ~wr_err;
assign cmd_hash_start_wd = reg_wdata[0];
- assign cmd_hash_process_we = addr_hit[4] && reg_we;
+ assign cmd_hash_process_we = addr_hit[4] & reg_we & ~wr_err;
assign cmd_hash_process_wd = reg_wdata[1];
assign status_fifo_empty_re = addr_hit[5] && reg_re;
@@ -1026,31 +1045,31 @@
assign status_fifo_depth_re = addr_hit[5] && reg_re;
- assign wipe_secret_we = addr_hit[6] && reg_we;
+ assign wipe_secret_we = addr_hit[6] & reg_we & ~wr_err;
assign wipe_secret_wd = reg_wdata[31:0];
- assign key0_we = addr_hit[7] && reg_we;
+ assign key0_we = addr_hit[7] & reg_we & ~wr_err;
assign key0_wd = reg_wdata[31:0];
- assign key1_we = addr_hit[8] && reg_we;
+ assign key1_we = addr_hit[8] & reg_we & ~wr_err;
assign key1_wd = reg_wdata[31:0];
- assign key2_we = addr_hit[9] && reg_we;
+ assign key2_we = addr_hit[9] & reg_we & ~wr_err;
assign key2_wd = reg_wdata[31:0];
- assign key3_we = addr_hit[10] && reg_we;
+ assign key3_we = addr_hit[10] & reg_we & ~wr_err;
assign key3_wd = reg_wdata[31:0];
- assign key4_we = addr_hit[11] && reg_we;
+ assign key4_we = addr_hit[11] & reg_we & ~wr_err;
assign key4_wd = reg_wdata[31:0];
- assign key5_we = addr_hit[12] && reg_we;
+ assign key5_we = addr_hit[12] & reg_we & ~wr_err;
assign key5_wd = reg_wdata[31:0];
- assign key6_we = addr_hit[13] && reg_we;
+ assign key6_we = addr_hit[13] & reg_we & ~wr_err;
assign key6_wd = reg_wdata[31:0];
- assign key7_we = addr_hit[14] && reg_we;
+ assign key7_we = addr_hit[14] & reg_we & ~wr_err;
assign key7_wd = reg_wdata[31:0];
assign digest0_re = addr_hit[15] && reg_re;
diff --git a/hw/ip/rv_plic/rtl/rv_plic_reg_pkg.sv b/hw/ip/rv_plic/rtl/rv_plic_reg_pkg.sv
index 0b2b83c..8e5f6bd 100644
--- a/hw/ip/rv_plic/rtl/rv_plic_reg_pkg.sv
+++ b/hw/ip/rv_plic/rtl/rv_plic_reg_pkg.sv
@@ -493,4 +493,88 @@
parameter RV_PLIC_MSIP0_OFFSET = 9'h 10c;
+ // Register Index
+ typedef enum int {
+ RV_PLIC_IP,
+ RV_PLIC_LE,
+ RV_PLIC_PRIO0,
+ RV_PLIC_PRIO1,
+ RV_PLIC_PRIO2,
+ RV_PLIC_PRIO3,
+ RV_PLIC_PRIO4,
+ RV_PLIC_PRIO5,
+ RV_PLIC_PRIO6,
+ RV_PLIC_PRIO7,
+ RV_PLIC_PRIO8,
+ RV_PLIC_PRIO9,
+ RV_PLIC_PRIO10,
+ RV_PLIC_PRIO11,
+ RV_PLIC_PRIO12,
+ RV_PLIC_PRIO13,
+ RV_PLIC_PRIO14,
+ RV_PLIC_PRIO15,
+ RV_PLIC_PRIO16,
+ RV_PLIC_PRIO17,
+ RV_PLIC_PRIO18,
+ RV_PLIC_PRIO19,
+ RV_PLIC_PRIO20,
+ RV_PLIC_PRIO21,
+ RV_PLIC_PRIO22,
+ RV_PLIC_PRIO23,
+ RV_PLIC_PRIO24,
+ RV_PLIC_PRIO25,
+ RV_PLIC_PRIO26,
+ RV_PLIC_PRIO27,
+ RV_PLIC_PRIO28,
+ RV_PLIC_PRIO29,
+ RV_PLIC_PRIO30,
+ RV_PLIC_PRIO31,
+ RV_PLIC_IE0,
+ RV_PLIC_THRESHOLD0,
+ RV_PLIC_CC0,
+ RV_PLIC_MSIP0
+ } rv_plic_id_e;
+
+ // Register width information to check illegal writes
+ localparam logic [3:0] RV_PLIC_PERMIT [38] = '{
+ 4'b 1111, // index[ 0] RV_PLIC_IP
+ 4'b 1111, // index[ 1] RV_PLIC_LE
+ 4'b 0001, // index[ 2] RV_PLIC_PRIO0
+ 4'b 0001, // index[ 3] RV_PLIC_PRIO1
+ 4'b 0001, // index[ 4] RV_PLIC_PRIO2
+ 4'b 0001, // index[ 5] RV_PLIC_PRIO3
+ 4'b 0001, // index[ 6] RV_PLIC_PRIO4
+ 4'b 0001, // index[ 7] RV_PLIC_PRIO5
+ 4'b 0001, // index[ 8] RV_PLIC_PRIO6
+ 4'b 0001, // index[ 9] RV_PLIC_PRIO7
+ 4'b 0001, // index[10] RV_PLIC_PRIO8
+ 4'b 0001, // index[11] RV_PLIC_PRIO9
+ 4'b 0001, // index[12] RV_PLIC_PRIO10
+ 4'b 0001, // index[13] RV_PLIC_PRIO11
+ 4'b 0001, // index[14] RV_PLIC_PRIO12
+ 4'b 0001, // index[15] RV_PLIC_PRIO13
+ 4'b 0001, // index[16] RV_PLIC_PRIO14
+ 4'b 0001, // index[17] RV_PLIC_PRIO15
+ 4'b 0001, // index[18] RV_PLIC_PRIO16
+ 4'b 0001, // index[19] RV_PLIC_PRIO17
+ 4'b 0001, // index[20] RV_PLIC_PRIO18
+ 4'b 0001, // index[21] RV_PLIC_PRIO19
+ 4'b 0001, // index[22] RV_PLIC_PRIO20
+ 4'b 0001, // index[23] RV_PLIC_PRIO21
+ 4'b 0001, // index[24] RV_PLIC_PRIO22
+ 4'b 0001, // index[25] RV_PLIC_PRIO23
+ 4'b 0001, // index[26] RV_PLIC_PRIO24
+ 4'b 0001, // index[27] RV_PLIC_PRIO25
+ 4'b 0001, // index[28] RV_PLIC_PRIO26
+ 4'b 0001, // index[29] RV_PLIC_PRIO27
+ 4'b 0001, // index[30] RV_PLIC_PRIO28
+ 4'b 0001, // index[31] RV_PLIC_PRIO29
+ 4'b 0001, // index[32] RV_PLIC_PRIO30
+ 4'b 0001, // index[33] RV_PLIC_PRIO31
+ 4'b 1111, // index[34] RV_PLIC_IE0
+ 4'b 0001, // index[35] RV_PLIC_THRESHOLD0
+ 4'b 0001, // index[36] RV_PLIC_CC0
+ 4'b 0001, // index[37] RV_PLIC_MSIP0
+ };
endpackage
+
diff --git a/hw/ip/rv_plic/rtl/rv_plic_reg_top.sv b/hw/ip/rv_plic/rtl/rv_plic_reg_top.sv
index 6e10442..e29b89f 100644
--- a/hw/ip/rv_plic/rtl/rv_plic_reg_top.sv
+++ b/hw/ip/rv_plic/rtl/rv_plic_reg_top.sv
@@ -32,7 +32,7 @@
logic [DW-1:0] reg_rdata;
logic reg_error;
- logic malformed, addrmiss;
+ logic addrmiss, wr_err;
logic [DW-1:0] reg_rdata_next;
@@ -62,16 +62,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = malformed | addrmiss ;
-
- // Malformed request check only affects to the write access
- always_comb begin : malformed_check
- if (reg_we && (reg_be != '1)) begin
- malformed = 1'b1;
- end else begin
- malformed = 1'b0;
- end
- end
+ assign reg_error = addrmiss | wr_err;
// TODO(eunchan): Revise Register Interface logic after REG INTF finalized
// TODO(eunchan): Make concrete scenario
@@ -3832,16 +3823,16 @@
logic [37:0] addr_hit;
always_comb begin
addr_hit = '0;
- addr_hit[0] = (reg_addr == RV_PLIC_IP_OFFSET);
- addr_hit[1] = (reg_addr == RV_PLIC_LE_OFFSET);
- addr_hit[2] = (reg_addr == RV_PLIC_PRIO0_OFFSET);
- addr_hit[3] = (reg_addr == RV_PLIC_PRIO1_OFFSET);
- addr_hit[4] = (reg_addr == RV_PLIC_PRIO2_OFFSET);
- addr_hit[5] = (reg_addr == RV_PLIC_PRIO3_OFFSET);
- addr_hit[6] = (reg_addr == RV_PLIC_PRIO4_OFFSET);
- addr_hit[7] = (reg_addr == RV_PLIC_PRIO5_OFFSET);
- addr_hit[8] = (reg_addr == RV_PLIC_PRIO6_OFFSET);
- addr_hit[9] = (reg_addr == RV_PLIC_PRIO7_OFFSET);
+ addr_hit[ 0] = (reg_addr == RV_PLIC_IP_OFFSET);
+ addr_hit[ 1] = (reg_addr == RV_PLIC_LE_OFFSET);
+ addr_hit[ 2] = (reg_addr == RV_PLIC_PRIO0_OFFSET);
+ addr_hit[ 3] = (reg_addr == RV_PLIC_PRIO1_OFFSET);
+ addr_hit[ 4] = (reg_addr == RV_PLIC_PRIO2_OFFSET);
+ addr_hit[ 5] = (reg_addr == RV_PLIC_PRIO3_OFFSET);
+ addr_hit[ 6] = (reg_addr == RV_PLIC_PRIO4_OFFSET);
+ addr_hit[ 7] = (reg_addr == RV_PLIC_PRIO5_OFFSET);
+ addr_hit[ 8] = (reg_addr == RV_PLIC_PRIO6_OFFSET);
+ addr_hit[ 9] = (reg_addr == RV_PLIC_PRIO7_OFFSET);
addr_hit[10] = (reg_addr == RV_PLIC_PRIO8_OFFSET);
addr_hit[11] = (reg_addr == RV_PLIC_PRIO9_OFFSET);
addr_hit[12] = (reg_addr == RV_PLIC_PRIO10_OFFSET);
@@ -3880,7 +3871,48 @@
end
end
- // Write Enable signal
+ // Check sub-word write is permitted
+ always_comb begin
+ wr_err = 1'b0;
+ if (addr_hit[ 0] && reg_we && (RV_PLIC_PERMIT[ 0] != (RV_PLIC_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 1] && reg_we && (RV_PLIC_PERMIT[ 1] != (RV_PLIC_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 2] && reg_we && (RV_PLIC_PERMIT[ 2] != (RV_PLIC_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 3] && reg_we && (RV_PLIC_PERMIT[ 3] != (RV_PLIC_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 4] && reg_we && (RV_PLIC_PERMIT[ 4] != (RV_PLIC_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 5] && reg_we && (RV_PLIC_PERMIT[ 5] != (RV_PLIC_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 6] && reg_we && (RV_PLIC_PERMIT[ 6] != (RV_PLIC_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 7] && reg_we && (RV_PLIC_PERMIT[ 7] != (RV_PLIC_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 8] && reg_we && (RV_PLIC_PERMIT[ 8] != (RV_PLIC_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 9] && reg_we && (RV_PLIC_PERMIT[ 9] != (RV_PLIC_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[10] && reg_we && (RV_PLIC_PERMIT[10] != (RV_PLIC_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[11] && reg_we && (RV_PLIC_PERMIT[11] != (RV_PLIC_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[12] && reg_we && (RV_PLIC_PERMIT[12] != (RV_PLIC_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[13] && reg_we && (RV_PLIC_PERMIT[13] != (RV_PLIC_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[14] && reg_we && (RV_PLIC_PERMIT[14] != (RV_PLIC_PERMIT[14] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[15] && reg_we && (RV_PLIC_PERMIT[15] != (RV_PLIC_PERMIT[15] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[16] && reg_we && (RV_PLIC_PERMIT[16] != (RV_PLIC_PERMIT[16] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[17] && reg_we && (RV_PLIC_PERMIT[17] != (RV_PLIC_PERMIT[17] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[18] && reg_we && (RV_PLIC_PERMIT[18] != (RV_PLIC_PERMIT[18] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[19] && reg_we && (RV_PLIC_PERMIT[19] != (RV_PLIC_PERMIT[19] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[20] && reg_we && (RV_PLIC_PERMIT[20] != (RV_PLIC_PERMIT[20] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[21] && reg_we && (RV_PLIC_PERMIT[21] != (RV_PLIC_PERMIT[21] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[22] && reg_we && (RV_PLIC_PERMIT[22] != (RV_PLIC_PERMIT[22] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[23] && reg_we && (RV_PLIC_PERMIT[23] != (RV_PLIC_PERMIT[23] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[24] && reg_we && (RV_PLIC_PERMIT[24] != (RV_PLIC_PERMIT[24] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[25] && reg_we && (RV_PLIC_PERMIT[25] != (RV_PLIC_PERMIT[25] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[26] && reg_we && (RV_PLIC_PERMIT[26] != (RV_PLIC_PERMIT[26] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[27] && reg_we && (RV_PLIC_PERMIT[27] != (RV_PLIC_PERMIT[27] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[28] && reg_we && (RV_PLIC_PERMIT[28] != (RV_PLIC_PERMIT[28] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[29] && reg_we && (RV_PLIC_PERMIT[29] != (RV_PLIC_PERMIT[29] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[30] && reg_we && (RV_PLIC_PERMIT[30] != (RV_PLIC_PERMIT[30] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[31] && reg_we && (RV_PLIC_PERMIT[31] != (RV_PLIC_PERMIT[31] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[32] && reg_we && (RV_PLIC_PERMIT[32] != (RV_PLIC_PERMIT[32] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[33] && reg_we && (RV_PLIC_PERMIT[33] != (RV_PLIC_PERMIT[33] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[34] && reg_we && (RV_PLIC_PERMIT[34] != (RV_PLIC_PERMIT[34] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[35] && reg_we && (RV_PLIC_PERMIT[35] != (RV_PLIC_PERMIT[35] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[36] && reg_we && (RV_PLIC_PERMIT[36] != (RV_PLIC_PERMIT[36] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[37] && reg_we && (RV_PLIC_PERMIT[37] != (RV_PLIC_PERMIT[37] & reg_be))) wr_err = 1'b1 ;
+ end
@@ -3914,302 +3946,302 @@
- assign le_le0_we = addr_hit[1] && reg_we;
+ assign le_le0_we = addr_hit[1] & reg_we & ~wr_err;
assign le_le0_wd = reg_wdata[0];
- assign le_le1_we = addr_hit[1] && reg_we;
+ assign le_le1_we = addr_hit[1] & reg_we & ~wr_err;
assign le_le1_wd = reg_wdata[1];
- assign le_le2_we = addr_hit[1] && reg_we;
+ assign le_le2_we = addr_hit[1] & reg_we & ~wr_err;
assign le_le2_wd = reg_wdata[2];
- assign le_le3_we = addr_hit[1] && reg_we;
+ assign le_le3_we = addr_hit[1] & reg_we & ~wr_err;
assign le_le3_wd = reg_wdata[3];
- assign le_le4_we = addr_hit[1] && reg_we;
+ assign le_le4_we = addr_hit[1] & reg_we & ~wr_err;
assign le_le4_wd = reg_wdata[4];
- assign le_le5_we = addr_hit[1] && reg_we;
+ assign le_le5_we = addr_hit[1] & reg_we & ~wr_err;
assign le_le5_wd = reg_wdata[5];
- assign le_le6_we = addr_hit[1] && reg_we;
+ assign le_le6_we = addr_hit[1] & reg_we & ~wr_err;
assign le_le6_wd = reg_wdata[6];
- assign le_le7_we = addr_hit[1] && reg_we;
+ assign le_le7_we = addr_hit[1] & reg_we & ~wr_err;
assign le_le7_wd = reg_wdata[7];
- assign le_le8_we = addr_hit[1] && reg_we;
+ assign le_le8_we = addr_hit[1] & reg_we & ~wr_err;
assign le_le8_wd = reg_wdata[8];
- assign le_le9_we = addr_hit[1] && reg_we;
+ assign le_le9_we = addr_hit[1] & reg_we & ~wr_err;
assign le_le9_wd = reg_wdata[9];
- assign le_le10_we = addr_hit[1] && reg_we;
+ assign le_le10_we = addr_hit[1] & reg_we & ~wr_err;
assign le_le10_wd = reg_wdata[10];
- assign le_le11_we = addr_hit[1] && reg_we;
+ assign le_le11_we = addr_hit[1] & reg_we & ~wr_err;
assign le_le11_wd = reg_wdata[11];
- assign le_le12_we = addr_hit[1] && reg_we;
+ assign le_le12_we = addr_hit[1] & reg_we & ~wr_err;
assign le_le12_wd = reg_wdata[12];
- assign le_le13_we = addr_hit[1] && reg_we;
+ assign le_le13_we = addr_hit[1] & reg_we & ~wr_err;
assign le_le13_wd = reg_wdata[13];
- assign le_le14_we = addr_hit[1] && reg_we;
+ assign le_le14_we = addr_hit[1] & reg_we & ~wr_err;
assign le_le14_wd = reg_wdata[14];
- assign le_le15_we = addr_hit[1] && reg_we;
+ assign le_le15_we = addr_hit[1] & reg_we & ~wr_err;
assign le_le15_wd = reg_wdata[15];
- assign le_le16_we = addr_hit[1] && reg_we;
+ assign le_le16_we = addr_hit[1] & reg_we & ~wr_err;
assign le_le16_wd = reg_wdata[16];
- assign le_le17_we = addr_hit[1] && reg_we;
+ assign le_le17_we = addr_hit[1] & reg_we & ~wr_err;
assign le_le17_wd = reg_wdata[17];
- assign le_le18_we = addr_hit[1] && reg_we;
+ assign le_le18_we = addr_hit[1] & reg_we & ~wr_err;
assign le_le18_wd = reg_wdata[18];
- assign le_le19_we = addr_hit[1] && reg_we;
+ assign le_le19_we = addr_hit[1] & reg_we & ~wr_err;
assign le_le19_wd = reg_wdata[19];
- assign le_le20_we = addr_hit[1] && reg_we;
+ assign le_le20_we = addr_hit[1] & reg_we & ~wr_err;
assign le_le20_wd = reg_wdata[20];
- assign le_le21_we = addr_hit[1] && reg_we;
+ assign le_le21_we = addr_hit[1] & reg_we & ~wr_err;
assign le_le21_wd = reg_wdata[21];
- assign le_le22_we = addr_hit[1] && reg_we;
+ assign le_le22_we = addr_hit[1] & reg_we & ~wr_err;
assign le_le22_wd = reg_wdata[22];
- assign le_le23_we = addr_hit[1] && reg_we;
+ assign le_le23_we = addr_hit[1] & reg_we & ~wr_err;
assign le_le23_wd = reg_wdata[23];
- assign le_le24_we = addr_hit[1] && reg_we;
+ assign le_le24_we = addr_hit[1] & reg_we & ~wr_err;
assign le_le24_wd = reg_wdata[24];
- assign le_le25_we = addr_hit[1] && reg_we;
+ assign le_le25_we = addr_hit[1] & reg_we & ~wr_err;
assign le_le25_wd = reg_wdata[25];
- assign le_le26_we = addr_hit[1] && reg_we;
+ assign le_le26_we = addr_hit[1] & reg_we & ~wr_err;
assign le_le26_wd = reg_wdata[26];
- assign le_le27_we = addr_hit[1] && reg_we;
+ assign le_le27_we = addr_hit[1] & reg_we & ~wr_err;
assign le_le27_wd = reg_wdata[27];
- assign le_le28_we = addr_hit[1] && reg_we;
+ assign le_le28_we = addr_hit[1] & reg_we & ~wr_err;
assign le_le28_wd = reg_wdata[28];
- assign le_le29_we = addr_hit[1] && reg_we;
+ assign le_le29_we = addr_hit[1] & reg_we & ~wr_err;
assign le_le29_wd = reg_wdata[29];
- assign le_le30_we = addr_hit[1] && reg_we;
+ assign le_le30_we = addr_hit[1] & reg_we & ~wr_err;
assign le_le30_wd = reg_wdata[30];
- assign le_le31_we = addr_hit[1] && reg_we;
+ assign le_le31_we = addr_hit[1] & reg_we & ~wr_err;
assign le_le31_wd = reg_wdata[31];
- assign prio0_we = addr_hit[2] && reg_we;
+ assign prio0_we = addr_hit[2] & reg_we & ~wr_err;
assign prio0_wd = reg_wdata[2:0];
- assign prio1_we = addr_hit[3] && reg_we;
+ assign prio1_we = addr_hit[3] & reg_we & ~wr_err;
assign prio1_wd = reg_wdata[2:0];
- assign prio2_we = addr_hit[4] && reg_we;
+ assign prio2_we = addr_hit[4] & reg_we & ~wr_err;
assign prio2_wd = reg_wdata[2:0];
- assign prio3_we = addr_hit[5] && reg_we;
+ assign prio3_we = addr_hit[5] & reg_we & ~wr_err;
assign prio3_wd = reg_wdata[2:0];
- assign prio4_we = addr_hit[6] && reg_we;
+ assign prio4_we = addr_hit[6] & reg_we & ~wr_err;
assign prio4_wd = reg_wdata[2:0];
- assign prio5_we = addr_hit[7] && reg_we;
+ assign prio5_we = addr_hit[7] & reg_we & ~wr_err;
assign prio5_wd = reg_wdata[2:0];
- assign prio6_we = addr_hit[8] && reg_we;
+ assign prio6_we = addr_hit[8] & reg_we & ~wr_err;
assign prio6_wd = reg_wdata[2:0];
- assign prio7_we = addr_hit[9] && reg_we;
+ assign prio7_we = addr_hit[9] & reg_we & ~wr_err;
assign prio7_wd = reg_wdata[2:0];
- assign prio8_we = addr_hit[10] && reg_we;
+ assign prio8_we = addr_hit[10] & reg_we & ~wr_err;
assign prio8_wd = reg_wdata[2:0];
- assign prio9_we = addr_hit[11] && reg_we;
+ assign prio9_we = addr_hit[11] & reg_we & ~wr_err;
assign prio9_wd = reg_wdata[2:0];
- assign prio10_we = addr_hit[12] && reg_we;
+ assign prio10_we = addr_hit[12] & reg_we & ~wr_err;
assign prio10_wd = reg_wdata[2:0];
- assign prio11_we = addr_hit[13] && reg_we;
+ assign prio11_we = addr_hit[13] & reg_we & ~wr_err;
assign prio11_wd = reg_wdata[2:0];
- assign prio12_we = addr_hit[14] && reg_we;
+ assign prio12_we = addr_hit[14] & reg_we & ~wr_err;
assign prio12_wd = reg_wdata[2:0];
- assign prio13_we = addr_hit[15] && reg_we;
+ assign prio13_we = addr_hit[15] & reg_we & ~wr_err;
assign prio13_wd = reg_wdata[2:0];
- assign prio14_we = addr_hit[16] && reg_we;
+ assign prio14_we = addr_hit[16] & reg_we & ~wr_err;
assign prio14_wd = reg_wdata[2:0];
- assign prio15_we = addr_hit[17] && reg_we;
+ assign prio15_we = addr_hit[17] & reg_we & ~wr_err;
assign prio15_wd = reg_wdata[2:0];
- assign prio16_we = addr_hit[18] && reg_we;
+ assign prio16_we = addr_hit[18] & reg_we & ~wr_err;
assign prio16_wd = reg_wdata[2:0];
- assign prio17_we = addr_hit[19] && reg_we;
+ assign prio17_we = addr_hit[19] & reg_we & ~wr_err;
assign prio17_wd = reg_wdata[2:0];
- assign prio18_we = addr_hit[20] && reg_we;
+ assign prio18_we = addr_hit[20] & reg_we & ~wr_err;
assign prio18_wd = reg_wdata[2:0];
- assign prio19_we = addr_hit[21] && reg_we;
+ assign prio19_we = addr_hit[21] & reg_we & ~wr_err;
assign prio19_wd = reg_wdata[2:0];
- assign prio20_we = addr_hit[22] && reg_we;
+ assign prio20_we = addr_hit[22] & reg_we & ~wr_err;
assign prio20_wd = reg_wdata[2:0];
- assign prio21_we = addr_hit[23] && reg_we;
+ assign prio21_we = addr_hit[23] & reg_we & ~wr_err;
assign prio21_wd = reg_wdata[2:0];
- assign prio22_we = addr_hit[24] && reg_we;
+ assign prio22_we = addr_hit[24] & reg_we & ~wr_err;
assign prio22_wd = reg_wdata[2:0];
- assign prio23_we = addr_hit[25] && reg_we;
+ assign prio23_we = addr_hit[25] & reg_we & ~wr_err;
assign prio23_wd = reg_wdata[2:0];
- assign prio24_we = addr_hit[26] && reg_we;
+ assign prio24_we = addr_hit[26] & reg_we & ~wr_err;
assign prio24_wd = reg_wdata[2:0];
- assign prio25_we = addr_hit[27] && reg_we;
+ assign prio25_we = addr_hit[27] & reg_we & ~wr_err;
assign prio25_wd = reg_wdata[2:0];
- assign prio26_we = addr_hit[28] && reg_we;
+ assign prio26_we = addr_hit[28] & reg_we & ~wr_err;
assign prio26_wd = reg_wdata[2:0];
- assign prio27_we = addr_hit[29] && reg_we;
+ assign prio27_we = addr_hit[29] & reg_we & ~wr_err;
assign prio27_wd = reg_wdata[2:0];
- assign prio28_we = addr_hit[30] && reg_we;
+ assign prio28_we = addr_hit[30] & reg_we & ~wr_err;
assign prio28_wd = reg_wdata[2:0];
- assign prio29_we = addr_hit[31] && reg_we;
+ assign prio29_we = addr_hit[31] & reg_we & ~wr_err;
assign prio29_wd = reg_wdata[2:0];
- assign prio30_we = addr_hit[32] && reg_we;
+ assign prio30_we = addr_hit[32] & reg_we & ~wr_err;
assign prio30_wd = reg_wdata[2:0];
- assign prio31_we = addr_hit[33] && reg_we;
+ assign prio31_we = addr_hit[33] & reg_we & ~wr_err;
assign prio31_wd = reg_wdata[2:0];
- assign ie0_e0_we = addr_hit[34] && reg_we;
+ assign ie0_e0_we = addr_hit[34] & reg_we & ~wr_err;
assign ie0_e0_wd = reg_wdata[0];
- assign ie0_e1_we = addr_hit[34] && reg_we;
+ assign ie0_e1_we = addr_hit[34] & reg_we & ~wr_err;
assign ie0_e1_wd = reg_wdata[1];
- assign ie0_e2_we = addr_hit[34] && reg_we;
+ assign ie0_e2_we = addr_hit[34] & reg_we & ~wr_err;
assign ie0_e2_wd = reg_wdata[2];
- assign ie0_e3_we = addr_hit[34] && reg_we;
+ assign ie0_e3_we = addr_hit[34] & reg_we & ~wr_err;
assign ie0_e3_wd = reg_wdata[3];
- assign ie0_e4_we = addr_hit[34] && reg_we;
+ assign ie0_e4_we = addr_hit[34] & reg_we & ~wr_err;
assign ie0_e4_wd = reg_wdata[4];
- assign ie0_e5_we = addr_hit[34] && reg_we;
+ assign ie0_e5_we = addr_hit[34] & reg_we & ~wr_err;
assign ie0_e5_wd = reg_wdata[5];
- assign ie0_e6_we = addr_hit[34] && reg_we;
+ assign ie0_e6_we = addr_hit[34] & reg_we & ~wr_err;
assign ie0_e6_wd = reg_wdata[6];
- assign ie0_e7_we = addr_hit[34] && reg_we;
+ assign ie0_e7_we = addr_hit[34] & reg_we & ~wr_err;
assign ie0_e7_wd = reg_wdata[7];
- assign ie0_e8_we = addr_hit[34] && reg_we;
+ assign ie0_e8_we = addr_hit[34] & reg_we & ~wr_err;
assign ie0_e8_wd = reg_wdata[8];
- assign ie0_e9_we = addr_hit[34] && reg_we;
+ assign ie0_e9_we = addr_hit[34] & reg_we & ~wr_err;
assign ie0_e9_wd = reg_wdata[9];
- assign ie0_e10_we = addr_hit[34] && reg_we;
+ assign ie0_e10_we = addr_hit[34] & reg_we & ~wr_err;
assign ie0_e10_wd = reg_wdata[10];
- assign ie0_e11_we = addr_hit[34] && reg_we;
+ assign ie0_e11_we = addr_hit[34] & reg_we & ~wr_err;
assign ie0_e11_wd = reg_wdata[11];
- assign ie0_e12_we = addr_hit[34] && reg_we;
+ assign ie0_e12_we = addr_hit[34] & reg_we & ~wr_err;
assign ie0_e12_wd = reg_wdata[12];
- assign ie0_e13_we = addr_hit[34] && reg_we;
+ assign ie0_e13_we = addr_hit[34] & reg_we & ~wr_err;
assign ie0_e13_wd = reg_wdata[13];
- assign ie0_e14_we = addr_hit[34] && reg_we;
+ assign ie0_e14_we = addr_hit[34] & reg_we & ~wr_err;
assign ie0_e14_wd = reg_wdata[14];
- assign ie0_e15_we = addr_hit[34] && reg_we;
+ assign ie0_e15_we = addr_hit[34] & reg_we & ~wr_err;
assign ie0_e15_wd = reg_wdata[15];
- assign ie0_e16_we = addr_hit[34] && reg_we;
+ assign ie0_e16_we = addr_hit[34] & reg_we & ~wr_err;
assign ie0_e16_wd = reg_wdata[16];
- assign ie0_e17_we = addr_hit[34] && reg_we;
+ assign ie0_e17_we = addr_hit[34] & reg_we & ~wr_err;
assign ie0_e17_wd = reg_wdata[17];
- assign ie0_e18_we = addr_hit[34] && reg_we;
+ assign ie0_e18_we = addr_hit[34] & reg_we & ~wr_err;
assign ie0_e18_wd = reg_wdata[18];
- assign ie0_e19_we = addr_hit[34] && reg_we;
+ assign ie0_e19_we = addr_hit[34] & reg_we & ~wr_err;
assign ie0_e19_wd = reg_wdata[19];
- assign ie0_e20_we = addr_hit[34] && reg_we;
+ assign ie0_e20_we = addr_hit[34] & reg_we & ~wr_err;
assign ie0_e20_wd = reg_wdata[20];
- assign ie0_e21_we = addr_hit[34] && reg_we;
+ assign ie0_e21_we = addr_hit[34] & reg_we & ~wr_err;
assign ie0_e21_wd = reg_wdata[21];
- assign ie0_e22_we = addr_hit[34] && reg_we;
+ assign ie0_e22_we = addr_hit[34] & reg_we & ~wr_err;
assign ie0_e22_wd = reg_wdata[22];
- assign ie0_e23_we = addr_hit[34] && reg_we;
+ assign ie0_e23_we = addr_hit[34] & reg_we & ~wr_err;
assign ie0_e23_wd = reg_wdata[23];
- assign ie0_e24_we = addr_hit[34] && reg_we;
+ assign ie0_e24_we = addr_hit[34] & reg_we & ~wr_err;
assign ie0_e24_wd = reg_wdata[24];
- assign ie0_e25_we = addr_hit[34] && reg_we;
+ assign ie0_e25_we = addr_hit[34] & reg_we & ~wr_err;
assign ie0_e25_wd = reg_wdata[25];
- assign ie0_e26_we = addr_hit[34] && reg_we;
+ assign ie0_e26_we = addr_hit[34] & reg_we & ~wr_err;
assign ie0_e26_wd = reg_wdata[26];
- assign ie0_e27_we = addr_hit[34] && reg_we;
+ assign ie0_e27_we = addr_hit[34] & reg_we & ~wr_err;
assign ie0_e27_wd = reg_wdata[27];
- assign ie0_e28_we = addr_hit[34] && reg_we;
+ assign ie0_e28_we = addr_hit[34] & reg_we & ~wr_err;
assign ie0_e28_wd = reg_wdata[28];
- assign ie0_e29_we = addr_hit[34] && reg_we;
+ assign ie0_e29_we = addr_hit[34] & reg_we & ~wr_err;
assign ie0_e29_wd = reg_wdata[29];
- assign ie0_e30_we = addr_hit[34] && reg_we;
+ assign ie0_e30_we = addr_hit[34] & reg_we & ~wr_err;
assign ie0_e30_wd = reg_wdata[30];
- assign ie0_e31_we = addr_hit[34] && reg_we;
+ assign ie0_e31_we = addr_hit[34] & reg_we & ~wr_err;
assign ie0_e31_wd = reg_wdata[31];
- assign threshold0_we = addr_hit[35] && reg_we;
+ assign threshold0_we = addr_hit[35] & reg_we & ~wr_err;
assign threshold0_wd = reg_wdata[2:0];
- assign cc0_we = addr_hit[36] && reg_we;
+ assign cc0_we = addr_hit[36] & reg_we & ~wr_err;
assign cc0_wd = reg_wdata[5:0];
assign cc0_re = addr_hit[36] && reg_re;
- assign msip0_we = addr_hit[37] && reg_we;
+ assign msip0_we = addr_hit[37] & reg_we & ~wr_err;
assign msip0_wd = reg_wdata[0];
// Read data return
diff --git a/hw/ip/rv_timer/rtl/rv_timer_reg_pkg.sv b/hw/ip/rv_timer/rtl/rv_timer_reg_pkg.sv
index 8b856b8..7970a7f 100644
--- a/hw/ip/rv_timer/rtl/rv_timer_reg_pkg.sv
+++ b/hw/ip/rv_timer/rtl/rv_timer_reg_pkg.sv
@@ -73,4 +73,30 @@
parameter RV_TIMER_INTR_TEST0_OFFSET = 9'h 11c;
+ // Register Index
+ typedef enum int {
+ RV_TIMER_CTRL,
+ RV_TIMER_CFG0,
+ RV_TIMER_TIMER_V_LOWER0,
+ RV_TIMER_TIMER_V_UPPER0,
+ RV_TIMER_COMPARE_LOWER0_0,
+ RV_TIMER_COMPARE_UPPER0_0,
+ RV_TIMER_INTR_ENABLE0,
+ RV_TIMER_INTR_STATE0,
+ RV_TIMER_INTR_TEST0
+ } rv_timer_id_e;
+
+ // Register width information to check illegal writes
+ localparam logic [3:0] RV_TIMER_PERMIT [9] = '{
+ 4'b 0001, // index[0] RV_TIMER_CTRL
+ 4'b 1111, // index[1] RV_TIMER_CFG0
+ 4'b 1111, // index[2] RV_TIMER_TIMER_V_LOWER0
+ 4'b 1111, // index[3] RV_TIMER_TIMER_V_UPPER0
+ 4'b 1111, // index[4] RV_TIMER_COMPARE_LOWER0_0
+ 4'b 1111, // index[5] RV_TIMER_COMPARE_UPPER0_0
+ 4'b 0001, // index[6] RV_TIMER_INTR_ENABLE0
+ 4'b 0001, // index[7] RV_TIMER_INTR_STATE0
+ 4'b 0001, // index[8] RV_TIMER_INTR_TEST0
+ };
endpackage
+
diff --git a/hw/ip/rv_timer/rtl/rv_timer_reg_top.sv b/hw/ip/rv_timer/rtl/rv_timer_reg_top.sv
index 9f6a36a..0bd6647 100644
--- a/hw/ip/rv_timer/rtl/rv_timer_reg_top.sv
+++ b/hw/ip/rv_timer/rtl/rv_timer_reg_top.sv
@@ -32,7 +32,7 @@
logic [DW-1:0] reg_rdata;
logic reg_error;
- logic malformed, addrmiss;
+ logic addrmiss, wr_err;
logic [DW-1:0] reg_rdata_next;
@@ -62,16 +62,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = malformed | addrmiss ;
-
- // Malformed request check only affects to the write access
- always_comb begin : malformed_check
- if (reg_we && (reg_be != '1)) begin
- malformed = 1'b1;
- end else begin
- malformed = 1'b0;
- end
- end
+ assign reg_error = addrmiss | wr_err;
// TODO(eunchan): Revise Register Interface logic after REG INTF finalized
// TODO(eunchan): Make concrete scenario
@@ -405,36 +396,48 @@
end
end
- // Write Enable signal
+ // Check sub-word write is permitted
+ always_comb begin
+ wr_err = 1'b0;
+ if (addr_hit[0] && reg_we && (RV_TIMER_PERMIT[0] != (RV_TIMER_PERMIT[0] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[1] && reg_we && (RV_TIMER_PERMIT[1] != (RV_TIMER_PERMIT[1] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[2] && reg_we && (RV_TIMER_PERMIT[2] != (RV_TIMER_PERMIT[2] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[3] && reg_we && (RV_TIMER_PERMIT[3] != (RV_TIMER_PERMIT[3] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[4] && reg_we && (RV_TIMER_PERMIT[4] != (RV_TIMER_PERMIT[4] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[5] && reg_we && (RV_TIMER_PERMIT[5] != (RV_TIMER_PERMIT[5] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[6] && reg_we && (RV_TIMER_PERMIT[6] != (RV_TIMER_PERMIT[6] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[7] && reg_we && (RV_TIMER_PERMIT[7] != (RV_TIMER_PERMIT[7] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[8] && reg_we && (RV_TIMER_PERMIT[8] != (RV_TIMER_PERMIT[8] & reg_be))) wr_err = 1'b1 ;
+ end
- assign ctrl_we = addr_hit[0] && reg_we;
+ assign ctrl_we = addr_hit[0] & reg_we & ~wr_err;
assign ctrl_wd = reg_wdata[0];
- assign cfg0_prescale_we = addr_hit[1] && reg_we;
+ assign cfg0_prescale_we = addr_hit[1] & reg_we & ~wr_err;
assign cfg0_prescale_wd = reg_wdata[11:0];
- assign cfg0_step_we = addr_hit[1] && reg_we;
+ assign cfg0_step_we = addr_hit[1] & reg_we & ~wr_err;
assign cfg0_step_wd = reg_wdata[23:16];
- assign timer_v_lower0_we = addr_hit[2] && reg_we;
+ assign timer_v_lower0_we = addr_hit[2] & reg_we & ~wr_err;
assign timer_v_lower0_wd = reg_wdata[31:0];
- assign timer_v_upper0_we = addr_hit[3] && reg_we;
+ assign timer_v_upper0_we = addr_hit[3] & reg_we & ~wr_err;
assign timer_v_upper0_wd = reg_wdata[31:0];
- assign compare_lower0_0_we = addr_hit[4] && reg_we;
+ assign compare_lower0_0_we = addr_hit[4] & reg_we & ~wr_err;
assign compare_lower0_0_wd = reg_wdata[31:0];
- assign compare_upper0_0_we = addr_hit[5] && reg_we;
+ assign compare_upper0_0_we = addr_hit[5] & reg_we & ~wr_err;
assign compare_upper0_0_wd = reg_wdata[31:0];
- assign intr_enable0_we = addr_hit[6] && reg_we;
+ assign intr_enable0_we = addr_hit[6] & reg_we & ~wr_err;
assign intr_enable0_wd = reg_wdata[0];
- assign intr_state0_we = addr_hit[7] && reg_we;
+ assign intr_state0_we = addr_hit[7] & reg_we & ~wr_err;
assign intr_state0_wd = reg_wdata[0];
- assign intr_test0_we = addr_hit[8] && reg_we;
+ assign intr_test0_we = addr_hit[8] & reg_we & ~wr_err;
assign intr_test0_wd = reg_wdata[0];
// Read data return
diff --git a/hw/ip/spi_device/rtl/spi_device_reg_pkg.sv b/hw/ip/spi_device/rtl/spi_device_reg_pkg.sv
index 727ef6b..c312ab3 100644
--- a/hw/ip/spi_device/rtl/spi_device_reg_pkg.sv
+++ b/hw/ip/spi_device/rtl/spi_device_reg_pkg.sv
@@ -200,4 +200,36 @@
parameter SPI_DEVICE_BUFFER_OFFSET = 12'h 800;
parameter SPI_DEVICE_BUFFER_SIZE = 12'h 800;
+ // Register Index
+ typedef enum int {
+ SPI_DEVICE_INTR_STATE,
+ SPI_DEVICE_INTR_ENABLE,
+ SPI_DEVICE_INTR_TEST,
+ SPI_DEVICE_CONTROL,
+ SPI_DEVICE_CFG,
+ SPI_DEVICE_FIFO_LEVEL,
+ SPI_DEVICE_ASYNC_FIFO_LEVEL,
+ SPI_DEVICE_STATUS,
+ SPI_DEVICE_RXF_PTR,
+ SPI_DEVICE_TXF_PTR,
+ SPI_DEVICE_RXF_ADDR,
+ SPI_DEVICE_TXF_ADDR
+ } spi_device_id_e;
+
+ // Register width information to check illegal writes
+ localparam logic [3:0] SPI_DEVICE_PERMIT [12] = '{
+ 4'b 0001, // index[ 0] SPI_DEVICE_INTR_STATE
+ 4'b 0001, // index[ 1] SPI_DEVICE_INTR_ENABLE
+ 4'b 0001, // index[ 2] SPI_DEVICE_INTR_TEST
+ 4'b 1111, // index[ 3] SPI_DEVICE_CONTROL
+ 4'b 0011, // index[ 4] SPI_DEVICE_CFG
+ 4'b 1111, // index[ 5] SPI_DEVICE_FIFO_LEVEL
+ 4'b 1111, // index[ 6] SPI_DEVICE_ASYNC_FIFO_LEVEL
+ 4'b 0001, // index[ 7] SPI_DEVICE_STATUS
+ 4'b 1111, // index[ 8] SPI_DEVICE_RXF_PTR
+ 4'b 1111, // index[ 9] SPI_DEVICE_TXF_PTR
+ 4'b 1111, // index[10] SPI_DEVICE_RXF_ADDR
+ 4'b 1111, // index[11] SPI_DEVICE_TXF_ADDR
+ };
endpackage
+
diff --git a/hw/ip/spi_device/rtl/spi_device_reg_top.sv b/hw/ip/spi_device/rtl/spi_device_reg_top.sv
index 9105c49..ae3a476 100644
--- a/hw/ip/spi_device/rtl/spi_device_reg_top.sv
+++ b/hw/ip/spi_device/rtl/spi_device_reg_top.sv
@@ -37,7 +37,7 @@
logic [DW-1:0] reg_rdata;
logic reg_error;
- logic malformed, addrmiss;
+ logic addrmiss, wr_err;
logic [DW-1:0] reg_rdata_next;
@@ -108,16 +108,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = malformed | addrmiss ;
-
- // Malformed request check only affects to the write access
- always_comb begin : malformed_check
- if (reg_we && (reg_be != '1)) begin
- malformed = 1'b1;
- end else begin
- malformed = 1'b0;
- end
- end
+ assign reg_error = addrmiss | wr_err;
// TODO(eunchan): Revise Register Interface logic after REG INTF finalized
// TODO(eunchan): Make concrete scenario
@@ -1132,16 +1123,16 @@
logic [11:0] addr_hit;
always_comb begin
addr_hit = '0;
- addr_hit[0] = (reg_addr == SPI_DEVICE_INTR_STATE_OFFSET);
- addr_hit[1] = (reg_addr == SPI_DEVICE_INTR_ENABLE_OFFSET);
- addr_hit[2] = (reg_addr == SPI_DEVICE_INTR_TEST_OFFSET);
- addr_hit[3] = (reg_addr == SPI_DEVICE_CONTROL_OFFSET);
- addr_hit[4] = (reg_addr == SPI_DEVICE_CFG_OFFSET);
- addr_hit[5] = (reg_addr == SPI_DEVICE_FIFO_LEVEL_OFFSET);
- addr_hit[6] = (reg_addr == SPI_DEVICE_ASYNC_FIFO_LEVEL_OFFSET);
- addr_hit[7] = (reg_addr == SPI_DEVICE_STATUS_OFFSET);
- addr_hit[8] = (reg_addr == SPI_DEVICE_RXF_PTR_OFFSET);
- addr_hit[9] = (reg_addr == SPI_DEVICE_TXF_PTR_OFFSET);
+ addr_hit[ 0] = (reg_addr == SPI_DEVICE_INTR_STATE_OFFSET);
+ addr_hit[ 1] = (reg_addr == SPI_DEVICE_INTR_ENABLE_OFFSET);
+ addr_hit[ 2] = (reg_addr == SPI_DEVICE_INTR_TEST_OFFSET);
+ addr_hit[ 3] = (reg_addr == SPI_DEVICE_CONTROL_OFFSET);
+ addr_hit[ 4] = (reg_addr == SPI_DEVICE_CFG_OFFSET);
+ addr_hit[ 5] = (reg_addr == SPI_DEVICE_FIFO_LEVEL_OFFSET);
+ addr_hit[ 6] = (reg_addr == SPI_DEVICE_ASYNC_FIFO_LEVEL_OFFSET);
+ addr_hit[ 7] = (reg_addr == SPI_DEVICE_STATUS_OFFSET);
+ addr_hit[ 8] = (reg_addr == SPI_DEVICE_RXF_PTR_OFFSET);
+ addr_hit[ 9] = (reg_addr == SPI_DEVICE_TXF_PTR_OFFSET);
addr_hit[10] = (reg_addr == SPI_DEVICE_RXF_ADDR_OFFSET);
addr_hit[11] = (reg_addr == SPI_DEVICE_TXF_ADDR_OFFSET);
end
@@ -1154,75 +1145,90 @@
end
end
- // Write Enable signal
+ // Check sub-word write is permitted
+ always_comb begin
+ wr_err = 1'b0;
+ if (addr_hit[ 0] && reg_we && (SPI_DEVICE_PERMIT[ 0] != (SPI_DEVICE_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 1] && reg_we && (SPI_DEVICE_PERMIT[ 1] != (SPI_DEVICE_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 2] && reg_we && (SPI_DEVICE_PERMIT[ 2] != (SPI_DEVICE_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 3] && reg_we && (SPI_DEVICE_PERMIT[ 3] != (SPI_DEVICE_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 4] && reg_we && (SPI_DEVICE_PERMIT[ 4] != (SPI_DEVICE_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 5] && reg_we && (SPI_DEVICE_PERMIT[ 5] != (SPI_DEVICE_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 6] && reg_we && (SPI_DEVICE_PERMIT[ 6] != (SPI_DEVICE_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 7] && reg_we && (SPI_DEVICE_PERMIT[ 7] != (SPI_DEVICE_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 8] && reg_we && (SPI_DEVICE_PERMIT[ 8] != (SPI_DEVICE_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 9] && reg_we && (SPI_DEVICE_PERMIT[ 9] != (SPI_DEVICE_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[10] && reg_we && (SPI_DEVICE_PERMIT[10] != (SPI_DEVICE_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[11] && reg_we && (SPI_DEVICE_PERMIT[11] != (SPI_DEVICE_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
+ end
- assign intr_state_rxf_we = addr_hit[0] && reg_we;
+ assign intr_state_rxf_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_rxf_wd = reg_wdata[0];
- assign intr_state_rxlvl_we = addr_hit[0] && reg_we;
+ assign intr_state_rxlvl_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_rxlvl_wd = reg_wdata[1];
- assign intr_state_txlvl_we = addr_hit[0] && reg_we;
+ assign intr_state_txlvl_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_txlvl_wd = reg_wdata[2];
- assign intr_state_rxerr_we = addr_hit[0] && reg_we;
+ assign intr_state_rxerr_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_rxerr_wd = reg_wdata[3];
- assign intr_enable_rxf_we = addr_hit[1] && reg_we;
+ assign intr_enable_rxf_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_rxf_wd = reg_wdata[0];
- assign intr_enable_rxlvl_we = addr_hit[1] && reg_we;
+ assign intr_enable_rxlvl_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_rxlvl_wd = reg_wdata[1];
- assign intr_enable_txlvl_we = addr_hit[1] && reg_we;
+ assign intr_enable_txlvl_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_txlvl_wd = reg_wdata[2];
- assign intr_enable_rxerr_we = addr_hit[1] && reg_we;
+ assign intr_enable_rxerr_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_rxerr_wd = reg_wdata[3];
- assign intr_test_rxf_we = addr_hit[2] && reg_we;
+ assign intr_test_rxf_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_rxf_wd = reg_wdata[0];
- assign intr_test_rxlvl_we = addr_hit[2] && reg_we;
+ assign intr_test_rxlvl_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_rxlvl_wd = reg_wdata[1];
- assign intr_test_txlvl_we = addr_hit[2] && reg_we;
+ assign intr_test_txlvl_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_txlvl_wd = reg_wdata[2];
- assign intr_test_rxerr_we = addr_hit[2] && reg_we;
+ assign intr_test_rxerr_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_rxerr_wd = reg_wdata[3];
- assign control_abort_we = addr_hit[3] && reg_we;
+ assign control_abort_we = addr_hit[3] & reg_we & ~wr_err;
assign control_abort_wd = reg_wdata[0];
- assign control_mode_we = addr_hit[3] && reg_we;
+ assign control_mode_we = addr_hit[3] & reg_we & ~wr_err;
assign control_mode_wd = reg_wdata[5:4];
- assign control_rst_txfifo_we = addr_hit[3] && reg_we;
+ assign control_rst_txfifo_we = addr_hit[3] & reg_we & ~wr_err;
assign control_rst_txfifo_wd = reg_wdata[16];
- assign control_rst_rxfifo_we = addr_hit[3] && reg_we;
+ assign control_rst_rxfifo_we = addr_hit[3] & reg_we & ~wr_err;
assign control_rst_rxfifo_wd = reg_wdata[17];
- assign cfg_cpol_we = addr_hit[4] && reg_we;
+ assign cfg_cpol_we = addr_hit[4] & reg_we & ~wr_err;
assign cfg_cpol_wd = reg_wdata[0];
- assign cfg_cpha_we = addr_hit[4] && reg_we;
+ assign cfg_cpha_we = addr_hit[4] & reg_we & ~wr_err;
assign cfg_cpha_wd = reg_wdata[1];
- assign cfg_tx_order_we = addr_hit[4] && reg_we;
+ assign cfg_tx_order_we = addr_hit[4] & reg_we & ~wr_err;
assign cfg_tx_order_wd = reg_wdata[2];
- assign cfg_rx_order_we = addr_hit[4] && reg_we;
+ assign cfg_rx_order_we = addr_hit[4] & reg_we & ~wr_err;
assign cfg_rx_order_wd = reg_wdata[3];
- assign cfg_timer_v_we = addr_hit[4] && reg_we;
+ assign cfg_timer_v_we = addr_hit[4] & reg_we & ~wr_err;
assign cfg_timer_v_wd = reg_wdata[15:8];
- assign fifo_level_rxlvl_we = addr_hit[5] && reg_we;
+ assign fifo_level_rxlvl_we = addr_hit[5] & reg_we & ~wr_err;
assign fifo_level_rxlvl_wd = reg_wdata[15:0];
- assign fifo_level_txlvl_we = addr_hit[5] && reg_we;
+ assign fifo_level_txlvl_we = addr_hit[5] & reg_we & ~wr_err;
assign fifo_level_txlvl_wd = reg_wdata[31:16];
assign async_fifo_level_rxlvl_re = addr_hit[6] && reg_re;
@@ -1239,24 +1245,24 @@
assign status_abort_done_re = addr_hit[7] && reg_re;
- assign rxf_ptr_rptr_we = addr_hit[8] && reg_we;
+ assign rxf_ptr_rptr_we = addr_hit[8] & reg_we & ~wr_err;
assign rxf_ptr_rptr_wd = reg_wdata[15:0];
- assign txf_ptr_wptr_we = addr_hit[9] && reg_we;
+ assign txf_ptr_wptr_we = addr_hit[9] & reg_we & ~wr_err;
assign txf_ptr_wptr_wd = reg_wdata[31:16];
- assign rxf_addr_base_we = addr_hit[10] && reg_we;
+ assign rxf_addr_base_we = addr_hit[10] & reg_we & ~wr_err;
assign rxf_addr_base_wd = reg_wdata[15:0];
- assign rxf_addr_limit_we = addr_hit[10] && reg_we;
+ assign rxf_addr_limit_we = addr_hit[10] & reg_we & ~wr_err;
assign rxf_addr_limit_wd = reg_wdata[31:16];
- assign txf_addr_base_we = addr_hit[11] && reg_we;
+ assign txf_addr_base_we = addr_hit[11] & reg_we & ~wr_err;
assign txf_addr_base_wd = reg_wdata[15:0];
- assign txf_addr_limit_we = addr_hit[11] && reg_we;
+ assign txf_addr_limit_we = addr_hit[11] & reg_we & ~wr_err;
assign txf_addr_limit_wd = reg_wdata[31:16];
// Read data return
diff --git a/hw/ip/uart/rtl/uart_reg_pkg.sv b/hw/ip/uart/rtl/uart_reg_pkg.sv
index 87da079..dbe7701 100644
--- a/hw/ip/uart/rtl/uart_reg_pkg.sv
+++ b/hw/ip/uart/rtl/uart_reg_pkg.sv
@@ -292,4 +292,36 @@
parameter UART_TIMEOUT_CTRL_OFFSET = 6'h 2c;
+ // Register Index
+ typedef enum int {
+ UART_INTR_STATE,
+ UART_INTR_ENABLE,
+ UART_INTR_TEST,
+ UART_CTRL,
+ UART_STATUS,
+ UART_RDATA,
+ UART_WDATA,
+ UART_FIFO_CTRL,
+ UART_FIFO_STATUS,
+ UART_OVRD,
+ UART_VAL,
+ UART_TIMEOUT_CTRL
+ } uart_id_e;
+
+ // Register width information to check illegal writes
+ localparam logic [3:0] UART_PERMIT [12] = '{
+ 4'b 0001, // index[ 0] UART_INTR_STATE
+ 4'b 0001, // index[ 1] UART_INTR_ENABLE
+ 4'b 0001, // index[ 2] UART_INTR_TEST
+ 4'b 1111, // index[ 3] UART_CTRL
+ 4'b 0001, // index[ 4] UART_STATUS
+ 4'b 0001, // index[ 5] UART_RDATA
+ 4'b 0001, // index[ 6] UART_WDATA
+ 4'b 0001, // index[ 7] UART_FIFO_CTRL
+ 4'b 1111, // index[ 8] UART_FIFO_STATUS
+ 4'b 0001, // index[ 9] UART_OVRD
+ 4'b 0011, // index[10] UART_VAL
+ 4'b 1111, // index[11] UART_TIMEOUT_CTRL
+ };
endpackage
+
diff --git a/hw/ip/uart/rtl/uart_reg_top.sv b/hw/ip/uart/rtl/uart_reg_top.sv
index 0bfac0c..19949bb 100644
--- a/hw/ip/uart/rtl/uart_reg_top.sv
+++ b/hw/ip/uart/rtl/uart_reg_top.sv
@@ -32,7 +32,7 @@
logic [DW-1:0] reg_rdata;
logic reg_error;
- logic malformed, addrmiss;
+ logic addrmiss, wr_err;
logic [DW-1:0] reg_rdata_next;
@@ -62,16 +62,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = malformed | addrmiss ;
-
- // Malformed request check only affects to the write access
- always_comb begin : malformed_check
- if (reg_we && (reg_be != '1)) begin
- malformed = 1'b1;
- end else begin
- malformed = 1'b0;
- end
- end
+ assign reg_error = addrmiss | wr_err;
// TODO(eunchan): Revise Register Interface logic after REG INTF finalized
// TODO(eunchan): Make concrete scenario
@@ -1405,16 +1396,16 @@
logic [11:0] addr_hit;
always_comb begin
addr_hit = '0;
- addr_hit[0] = (reg_addr == UART_INTR_STATE_OFFSET);
- addr_hit[1] = (reg_addr == UART_INTR_ENABLE_OFFSET);
- addr_hit[2] = (reg_addr == UART_INTR_TEST_OFFSET);
- addr_hit[3] = (reg_addr == UART_CTRL_OFFSET);
- addr_hit[4] = (reg_addr == UART_STATUS_OFFSET);
- addr_hit[5] = (reg_addr == UART_RDATA_OFFSET);
- addr_hit[6] = (reg_addr == UART_WDATA_OFFSET);
- addr_hit[7] = (reg_addr == UART_FIFO_CTRL_OFFSET);
- addr_hit[8] = (reg_addr == UART_FIFO_STATUS_OFFSET);
- addr_hit[9] = (reg_addr == UART_OVRD_OFFSET);
+ addr_hit[ 0] = (reg_addr == UART_INTR_STATE_OFFSET);
+ addr_hit[ 1] = (reg_addr == UART_INTR_ENABLE_OFFSET);
+ addr_hit[ 2] = (reg_addr == UART_INTR_TEST_OFFSET);
+ addr_hit[ 3] = (reg_addr == UART_CTRL_OFFSET);
+ addr_hit[ 4] = (reg_addr == UART_STATUS_OFFSET);
+ addr_hit[ 5] = (reg_addr == UART_RDATA_OFFSET);
+ addr_hit[ 6] = (reg_addr == UART_WDATA_OFFSET);
+ addr_hit[ 7] = (reg_addr == UART_FIFO_CTRL_OFFSET);
+ addr_hit[ 8] = (reg_addr == UART_FIFO_STATUS_OFFSET);
+ addr_hit[ 9] = (reg_addr == UART_OVRD_OFFSET);
addr_hit[10] = (reg_addr == UART_VAL_OFFSET);
addr_hit[11] = (reg_addr == UART_TIMEOUT_CTRL_OFFSET);
end
@@ -1427,105 +1418,120 @@
end
end
- // Write Enable signal
+ // Check sub-word write is permitted
+ always_comb begin
+ wr_err = 1'b0;
+ if (addr_hit[ 0] && reg_we && (UART_PERMIT[ 0] != (UART_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 1] && reg_we && (UART_PERMIT[ 1] != (UART_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 2] && reg_we && (UART_PERMIT[ 2] != (UART_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 3] && reg_we && (UART_PERMIT[ 3] != (UART_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 4] && reg_we && (UART_PERMIT[ 4] != (UART_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 5] && reg_we && (UART_PERMIT[ 5] != (UART_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 6] && reg_we && (UART_PERMIT[ 6] != (UART_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 7] && reg_we && (UART_PERMIT[ 7] != (UART_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 8] && reg_we && (UART_PERMIT[ 8] != (UART_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 9] && reg_we && (UART_PERMIT[ 9] != (UART_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[10] && reg_we && (UART_PERMIT[10] != (UART_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[11] && reg_we && (UART_PERMIT[11] != (UART_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
+ end
- assign intr_state_tx_watermark_we = addr_hit[0] && reg_we;
+ assign intr_state_tx_watermark_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_tx_watermark_wd = reg_wdata[0];
- assign intr_state_rx_watermark_we = addr_hit[0] && reg_we;
+ assign intr_state_rx_watermark_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_rx_watermark_wd = reg_wdata[1];
- assign intr_state_tx_overflow_we = addr_hit[0] && reg_we;
+ assign intr_state_tx_overflow_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_tx_overflow_wd = reg_wdata[2];
- assign intr_state_rx_overflow_we = addr_hit[0] && reg_we;
+ assign intr_state_rx_overflow_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_rx_overflow_wd = reg_wdata[3];
- assign intr_state_rx_frame_err_we = addr_hit[0] && reg_we;
+ assign intr_state_rx_frame_err_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_rx_frame_err_wd = reg_wdata[4];
- assign intr_state_rx_break_err_we = addr_hit[0] && reg_we;
+ assign intr_state_rx_break_err_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_rx_break_err_wd = reg_wdata[5];
- assign intr_state_rx_timeout_we = addr_hit[0] && reg_we;
+ assign intr_state_rx_timeout_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_rx_timeout_wd = reg_wdata[6];
- assign intr_state_rx_parity_err_we = addr_hit[0] && reg_we;
+ assign intr_state_rx_parity_err_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_rx_parity_err_wd = reg_wdata[7];
- assign intr_enable_tx_watermark_we = addr_hit[1] && reg_we;
+ assign intr_enable_tx_watermark_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_tx_watermark_wd = reg_wdata[0];
- assign intr_enable_rx_watermark_we = addr_hit[1] && reg_we;
+ assign intr_enable_rx_watermark_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_rx_watermark_wd = reg_wdata[1];
- assign intr_enable_tx_overflow_we = addr_hit[1] && reg_we;
+ assign intr_enable_tx_overflow_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_tx_overflow_wd = reg_wdata[2];
- assign intr_enable_rx_overflow_we = addr_hit[1] && reg_we;
+ assign intr_enable_rx_overflow_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_rx_overflow_wd = reg_wdata[3];
- assign intr_enable_rx_frame_err_we = addr_hit[1] && reg_we;
+ assign intr_enable_rx_frame_err_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_rx_frame_err_wd = reg_wdata[4];
- assign intr_enable_rx_break_err_we = addr_hit[1] && reg_we;
+ assign intr_enable_rx_break_err_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_rx_break_err_wd = reg_wdata[5];
- assign intr_enable_rx_timeout_we = addr_hit[1] && reg_we;
+ assign intr_enable_rx_timeout_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_rx_timeout_wd = reg_wdata[6];
- assign intr_enable_rx_parity_err_we = addr_hit[1] && reg_we;
+ assign intr_enable_rx_parity_err_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_rx_parity_err_wd = reg_wdata[7];
- assign intr_test_tx_watermark_we = addr_hit[2] && reg_we;
+ assign intr_test_tx_watermark_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_tx_watermark_wd = reg_wdata[0];
- assign intr_test_rx_watermark_we = addr_hit[2] && reg_we;
+ assign intr_test_rx_watermark_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_rx_watermark_wd = reg_wdata[1];
- assign intr_test_tx_overflow_we = addr_hit[2] && reg_we;
+ assign intr_test_tx_overflow_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_tx_overflow_wd = reg_wdata[2];
- assign intr_test_rx_overflow_we = addr_hit[2] && reg_we;
+ assign intr_test_rx_overflow_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_rx_overflow_wd = reg_wdata[3];
- assign intr_test_rx_frame_err_we = addr_hit[2] && reg_we;
+ assign intr_test_rx_frame_err_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_rx_frame_err_wd = reg_wdata[4];
- assign intr_test_rx_break_err_we = addr_hit[2] && reg_we;
+ assign intr_test_rx_break_err_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_rx_break_err_wd = reg_wdata[5];
- assign intr_test_rx_timeout_we = addr_hit[2] && reg_we;
+ assign intr_test_rx_timeout_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_rx_timeout_wd = reg_wdata[6];
- assign intr_test_rx_parity_err_we = addr_hit[2] && reg_we;
+ assign intr_test_rx_parity_err_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_rx_parity_err_wd = reg_wdata[7];
- assign ctrl_tx_we = addr_hit[3] && reg_we;
+ assign ctrl_tx_we = addr_hit[3] & reg_we & ~wr_err;
assign ctrl_tx_wd = reg_wdata[0];
- assign ctrl_rx_we = addr_hit[3] && reg_we;
+ assign ctrl_rx_we = addr_hit[3] & reg_we & ~wr_err;
assign ctrl_rx_wd = reg_wdata[1];
- assign ctrl_nf_we = addr_hit[3] && reg_we;
+ assign ctrl_nf_we = addr_hit[3] & reg_we & ~wr_err;
assign ctrl_nf_wd = reg_wdata[2];
- assign ctrl_slpbk_we = addr_hit[3] && reg_we;
+ assign ctrl_slpbk_we = addr_hit[3] & reg_we & ~wr_err;
assign ctrl_slpbk_wd = reg_wdata[4];
- assign ctrl_llpbk_we = addr_hit[3] && reg_we;
+ assign ctrl_llpbk_we = addr_hit[3] & reg_we & ~wr_err;
assign ctrl_llpbk_wd = reg_wdata[5];
- assign ctrl_parity_en_we = addr_hit[3] && reg_we;
+ assign ctrl_parity_en_we = addr_hit[3] & reg_we & ~wr_err;
assign ctrl_parity_en_wd = reg_wdata[6];
- assign ctrl_parity_odd_we = addr_hit[3] && reg_we;
+ assign ctrl_parity_odd_we = addr_hit[3] & reg_we & ~wr_err;
assign ctrl_parity_odd_wd = reg_wdata[7];
- assign ctrl_rxblvl_we = addr_hit[3] && reg_we;
+ assign ctrl_rxblvl_we = addr_hit[3] & reg_we & ~wr_err;
assign ctrl_rxblvl_wd = reg_wdata[9:8];
- assign ctrl_nco_we = addr_hit[3] && reg_we;
+ assign ctrl_nco_we = addr_hit[3] & reg_we & ~wr_err;
assign ctrl_nco_wd = reg_wdata[31:16];
assign status_txfull_re = addr_hit[4] && reg_re;
@@ -1542,37 +1548,37 @@
assign rdata_re = addr_hit[5] && reg_re;
- assign wdata_we = addr_hit[6] && reg_we;
+ assign wdata_we = addr_hit[6] & reg_we & ~wr_err;
assign wdata_wd = reg_wdata[7:0];
- assign fifo_ctrl_rxrst_we = addr_hit[7] && reg_we;
+ assign fifo_ctrl_rxrst_we = addr_hit[7] & reg_we & ~wr_err;
assign fifo_ctrl_rxrst_wd = reg_wdata[0];
- assign fifo_ctrl_txrst_we = addr_hit[7] && reg_we;
+ assign fifo_ctrl_txrst_we = addr_hit[7] & reg_we & ~wr_err;
assign fifo_ctrl_txrst_wd = reg_wdata[1];
- assign fifo_ctrl_rxilvl_we = addr_hit[7] && reg_we;
+ assign fifo_ctrl_rxilvl_we = addr_hit[7] & reg_we & ~wr_err;
assign fifo_ctrl_rxilvl_wd = reg_wdata[4:2];
- assign fifo_ctrl_txilvl_we = addr_hit[7] && reg_we;
+ assign fifo_ctrl_txilvl_we = addr_hit[7] & reg_we & ~wr_err;
assign fifo_ctrl_txilvl_wd = reg_wdata[6:5];
assign fifo_status_txlvl_re = addr_hit[8] && reg_re;
assign fifo_status_rxlvl_re = addr_hit[8] && reg_re;
- assign ovrd_txen_we = addr_hit[9] && reg_we;
+ assign ovrd_txen_we = addr_hit[9] & reg_we & ~wr_err;
assign ovrd_txen_wd = reg_wdata[0];
- assign ovrd_txval_we = addr_hit[9] && reg_we;
+ assign ovrd_txval_we = addr_hit[9] & reg_we & ~wr_err;
assign ovrd_txval_wd = reg_wdata[1];
assign val_re = addr_hit[10] && reg_re;
- assign timeout_ctrl_val_we = addr_hit[11] && reg_we;
+ assign timeout_ctrl_val_we = addr_hit[11] & reg_we & ~wr_err;
assign timeout_ctrl_val_wd = reg_wdata[23:0];
- assign timeout_ctrl_en_we = addr_hit[11] && reg_we;
+ assign timeout_ctrl_en_we = addr_hit[11] & reg_we & ~wr_err;
assign timeout_ctrl_en_wd = reg_wdata[31];
// Read data return
diff --git a/hw/ip/usbuart/rtl/usbuart_reg_pkg.sv b/hw/ip/usbuart/rtl/usbuart_reg_pkg.sv
index aca7698..ade7035 100644
--- a/hw/ip/usbuart/rtl/usbuart_reg_pkg.sv
+++ b/hw/ip/usbuart/rtl/usbuart_reg_pkg.sv
@@ -298,4 +298,40 @@
parameter USBUART_USBPARAM_OFFSET = 6'h 34;
+ // Register Index
+ typedef enum int {
+ USBUART_INTR_STATE,
+ USBUART_INTR_ENABLE,
+ USBUART_INTR_TEST,
+ USBUART_CTRL,
+ USBUART_STATUS,
+ USBUART_RDATA,
+ USBUART_WDATA,
+ USBUART_FIFO_CTRL,
+ USBUART_FIFO_STATUS,
+ USBUART_OVRD,
+ USBUART_VAL,
+ USBUART_TIMEOUT_CTRL,
+ USBUART_USBSTAT,
+ USBUART_USBPARAM
+ } usbuart_id_e;
+
+ // Register width information to check illegal writes
+ localparam logic [3:0] USBUART_PERMIT [14] = '{
+ 4'b 0001, // index[ 0] USBUART_INTR_STATE
+ 4'b 0001, // index[ 1] USBUART_INTR_ENABLE
+ 4'b 0001, // index[ 2] USBUART_INTR_TEST
+ 4'b 1111, // index[ 3] USBUART_CTRL
+ 4'b 0001, // index[ 4] USBUART_STATUS
+ 4'b 0001, // index[ 5] USBUART_RDATA
+ 4'b 0001, // index[ 6] USBUART_WDATA
+ 4'b 0001, // index[ 7] USBUART_FIFO_CTRL
+ 4'b 1111, // index[ 8] USBUART_FIFO_STATUS
+ 4'b 0001, // index[ 9] USBUART_OVRD
+ 4'b 0011, // index[10] USBUART_VAL
+ 4'b 1111, // index[11] USBUART_TIMEOUT_CTRL
+ 4'b 1111, // index[12] USBUART_USBSTAT
+ 4'b 1111, // index[13] USBUART_USBPARAM
+ };
endpackage
+
diff --git a/hw/ip/usbuart/rtl/usbuart_reg_top.sv b/hw/ip/usbuart/rtl/usbuart_reg_top.sv
index 9efc656..d64d3e4 100644
--- a/hw/ip/usbuart/rtl/usbuart_reg_top.sv
+++ b/hw/ip/usbuart/rtl/usbuart_reg_top.sv
@@ -32,7 +32,7 @@
logic [DW-1:0] reg_rdata;
logic reg_error;
- logic malformed, addrmiss;
+ logic addrmiss, wr_err;
logic [DW-1:0] reg_rdata_next;
@@ -62,16 +62,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = malformed | addrmiss ;
-
- // Malformed request check only affects to the write access
- always_comb begin : malformed_check
- if (reg_we && (reg_be != '1)) begin
- malformed = 1'b1;
- end else begin
- malformed = 1'b0;
- end
- end
+ assign reg_error = addrmiss | wr_err;
// TODO(eunchan): Revise Register Interface logic after REG INTF finalized
// TODO(eunchan): Make concrete scenario
@@ -1515,16 +1506,16 @@
logic [13:0] addr_hit;
always_comb begin
addr_hit = '0;
- addr_hit[0] = (reg_addr == USBUART_INTR_STATE_OFFSET);
- addr_hit[1] = (reg_addr == USBUART_INTR_ENABLE_OFFSET);
- addr_hit[2] = (reg_addr == USBUART_INTR_TEST_OFFSET);
- addr_hit[3] = (reg_addr == USBUART_CTRL_OFFSET);
- addr_hit[4] = (reg_addr == USBUART_STATUS_OFFSET);
- addr_hit[5] = (reg_addr == USBUART_RDATA_OFFSET);
- addr_hit[6] = (reg_addr == USBUART_WDATA_OFFSET);
- addr_hit[7] = (reg_addr == USBUART_FIFO_CTRL_OFFSET);
- addr_hit[8] = (reg_addr == USBUART_FIFO_STATUS_OFFSET);
- addr_hit[9] = (reg_addr == USBUART_OVRD_OFFSET);
+ addr_hit[ 0] = (reg_addr == USBUART_INTR_STATE_OFFSET);
+ addr_hit[ 1] = (reg_addr == USBUART_INTR_ENABLE_OFFSET);
+ addr_hit[ 2] = (reg_addr == USBUART_INTR_TEST_OFFSET);
+ addr_hit[ 3] = (reg_addr == USBUART_CTRL_OFFSET);
+ addr_hit[ 4] = (reg_addr == USBUART_STATUS_OFFSET);
+ addr_hit[ 5] = (reg_addr == USBUART_RDATA_OFFSET);
+ addr_hit[ 6] = (reg_addr == USBUART_WDATA_OFFSET);
+ addr_hit[ 7] = (reg_addr == USBUART_FIFO_CTRL_OFFSET);
+ addr_hit[ 8] = (reg_addr == USBUART_FIFO_STATUS_OFFSET);
+ addr_hit[ 9] = (reg_addr == USBUART_OVRD_OFFSET);
addr_hit[10] = (reg_addr == USBUART_VAL_OFFSET);
addr_hit[11] = (reg_addr == USBUART_TIMEOUT_CTRL_OFFSET);
addr_hit[12] = (reg_addr == USBUART_USBSTAT_OFFSET);
@@ -1539,105 +1530,122 @@
end
end
- // Write Enable signal
+ // Check sub-word write is permitted
+ always_comb begin
+ wr_err = 1'b0;
+ if (addr_hit[ 0] && reg_we && (USBUART_PERMIT[ 0] != (USBUART_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 1] && reg_we && (USBUART_PERMIT[ 1] != (USBUART_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 2] && reg_we && (USBUART_PERMIT[ 2] != (USBUART_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 3] && reg_we && (USBUART_PERMIT[ 3] != (USBUART_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 4] && reg_we && (USBUART_PERMIT[ 4] != (USBUART_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 5] && reg_we && (USBUART_PERMIT[ 5] != (USBUART_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 6] && reg_we && (USBUART_PERMIT[ 6] != (USBUART_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 7] && reg_we && (USBUART_PERMIT[ 7] != (USBUART_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 8] && reg_we && (USBUART_PERMIT[ 8] != (USBUART_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 9] && reg_we && (USBUART_PERMIT[ 9] != (USBUART_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[10] && reg_we && (USBUART_PERMIT[10] != (USBUART_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[11] && reg_we && (USBUART_PERMIT[11] != (USBUART_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[12] && reg_we && (USBUART_PERMIT[12] != (USBUART_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[13] && reg_we && (USBUART_PERMIT[13] != (USBUART_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
+ end
- assign intr_state_tx_watermark_we = addr_hit[0] && reg_we;
+ assign intr_state_tx_watermark_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_tx_watermark_wd = reg_wdata[0];
- assign intr_state_rx_watermark_we = addr_hit[0] && reg_we;
+ assign intr_state_rx_watermark_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_rx_watermark_wd = reg_wdata[1];
- assign intr_state_tx_overflow_we = addr_hit[0] && reg_we;
+ assign intr_state_tx_overflow_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_tx_overflow_wd = reg_wdata[2];
- assign intr_state_rx_overflow_we = addr_hit[0] && reg_we;
+ assign intr_state_rx_overflow_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_rx_overflow_wd = reg_wdata[3];
- assign intr_state_rx_frame_err_we = addr_hit[0] && reg_we;
+ assign intr_state_rx_frame_err_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_rx_frame_err_wd = reg_wdata[4];
- assign intr_state_rx_break_err_we = addr_hit[0] && reg_we;
+ assign intr_state_rx_break_err_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_rx_break_err_wd = reg_wdata[5];
- assign intr_state_rx_timeout_we = addr_hit[0] && reg_we;
+ assign intr_state_rx_timeout_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_rx_timeout_wd = reg_wdata[6];
- assign intr_state_rx_parity_err_we = addr_hit[0] && reg_we;
+ assign intr_state_rx_parity_err_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_rx_parity_err_wd = reg_wdata[7];
- assign intr_enable_tx_watermark_we = addr_hit[1] && reg_we;
+ assign intr_enable_tx_watermark_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_tx_watermark_wd = reg_wdata[0];
- assign intr_enable_rx_watermark_we = addr_hit[1] && reg_we;
+ assign intr_enable_rx_watermark_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_rx_watermark_wd = reg_wdata[1];
- assign intr_enable_tx_overflow_we = addr_hit[1] && reg_we;
+ assign intr_enable_tx_overflow_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_tx_overflow_wd = reg_wdata[2];
- assign intr_enable_rx_overflow_we = addr_hit[1] && reg_we;
+ assign intr_enable_rx_overflow_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_rx_overflow_wd = reg_wdata[3];
- assign intr_enable_rx_frame_err_we = addr_hit[1] && reg_we;
+ assign intr_enable_rx_frame_err_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_rx_frame_err_wd = reg_wdata[4];
- assign intr_enable_rx_break_err_we = addr_hit[1] && reg_we;
+ assign intr_enable_rx_break_err_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_rx_break_err_wd = reg_wdata[5];
- assign intr_enable_rx_timeout_we = addr_hit[1] && reg_we;
+ assign intr_enable_rx_timeout_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_rx_timeout_wd = reg_wdata[6];
- assign intr_enable_rx_parity_err_we = addr_hit[1] && reg_we;
+ assign intr_enable_rx_parity_err_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_rx_parity_err_wd = reg_wdata[7];
- assign intr_test_tx_watermark_we = addr_hit[2] && reg_we;
+ assign intr_test_tx_watermark_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_tx_watermark_wd = reg_wdata[0];
- assign intr_test_rx_watermark_we = addr_hit[2] && reg_we;
+ assign intr_test_rx_watermark_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_rx_watermark_wd = reg_wdata[1];
- assign intr_test_tx_overflow_we = addr_hit[2] && reg_we;
+ assign intr_test_tx_overflow_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_tx_overflow_wd = reg_wdata[2];
- assign intr_test_rx_overflow_we = addr_hit[2] && reg_we;
+ assign intr_test_rx_overflow_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_rx_overflow_wd = reg_wdata[3];
- assign intr_test_rx_frame_err_we = addr_hit[2] && reg_we;
+ assign intr_test_rx_frame_err_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_rx_frame_err_wd = reg_wdata[4];
- assign intr_test_rx_break_err_we = addr_hit[2] && reg_we;
+ assign intr_test_rx_break_err_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_rx_break_err_wd = reg_wdata[5];
- assign intr_test_rx_timeout_we = addr_hit[2] && reg_we;
+ assign intr_test_rx_timeout_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_rx_timeout_wd = reg_wdata[6];
- assign intr_test_rx_parity_err_we = addr_hit[2] && reg_we;
+ assign intr_test_rx_parity_err_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_rx_parity_err_wd = reg_wdata[7];
- assign ctrl_tx_we = addr_hit[3] && reg_we;
+ assign ctrl_tx_we = addr_hit[3] & reg_we & ~wr_err;
assign ctrl_tx_wd = reg_wdata[0];
- assign ctrl_rx_we = addr_hit[3] && reg_we;
+ assign ctrl_rx_we = addr_hit[3] & reg_we & ~wr_err;
assign ctrl_rx_wd = reg_wdata[1];
- assign ctrl_nf_we = addr_hit[3] && reg_we;
+ assign ctrl_nf_we = addr_hit[3] & reg_we & ~wr_err;
assign ctrl_nf_wd = reg_wdata[2];
- assign ctrl_slpbk_we = addr_hit[3] && reg_we;
+ assign ctrl_slpbk_we = addr_hit[3] & reg_we & ~wr_err;
assign ctrl_slpbk_wd = reg_wdata[4];
- assign ctrl_llpbk_we = addr_hit[3] && reg_we;
+ assign ctrl_llpbk_we = addr_hit[3] & reg_we & ~wr_err;
assign ctrl_llpbk_wd = reg_wdata[5];
- assign ctrl_parity_en_we = addr_hit[3] && reg_we;
+ assign ctrl_parity_en_we = addr_hit[3] & reg_we & ~wr_err;
assign ctrl_parity_en_wd = reg_wdata[6];
- assign ctrl_parity_odd_we = addr_hit[3] && reg_we;
+ assign ctrl_parity_odd_we = addr_hit[3] & reg_we & ~wr_err;
assign ctrl_parity_odd_wd = reg_wdata[7];
- assign ctrl_rxblvl_we = addr_hit[3] && reg_we;
+ assign ctrl_rxblvl_we = addr_hit[3] & reg_we & ~wr_err;
assign ctrl_rxblvl_wd = reg_wdata[9:8];
- assign ctrl_nco_we = addr_hit[3] && reg_we;
+ assign ctrl_nco_we = addr_hit[3] & reg_we & ~wr_err;
assign ctrl_nco_wd = reg_wdata[31:16];
assign status_txfull_re = addr_hit[4] && reg_re;
@@ -1654,37 +1662,37 @@
assign rdata_re = addr_hit[5] && reg_re;
- assign wdata_we = addr_hit[6] && reg_we;
+ assign wdata_we = addr_hit[6] & reg_we & ~wr_err;
assign wdata_wd = reg_wdata[7:0];
- assign fifo_ctrl_rxrst_we = addr_hit[7] && reg_we;
+ assign fifo_ctrl_rxrst_we = addr_hit[7] & reg_we & ~wr_err;
assign fifo_ctrl_rxrst_wd = reg_wdata[0];
- assign fifo_ctrl_txrst_we = addr_hit[7] && reg_we;
+ assign fifo_ctrl_txrst_we = addr_hit[7] & reg_we & ~wr_err;
assign fifo_ctrl_txrst_wd = reg_wdata[1];
- assign fifo_ctrl_rxilvl_we = addr_hit[7] && reg_we;
+ assign fifo_ctrl_rxilvl_we = addr_hit[7] & reg_we & ~wr_err;
assign fifo_ctrl_rxilvl_wd = reg_wdata[4:2];
- assign fifo_ctrl_txilvl_we = addr_hit[7] && reg_we;
+ assign fifo_ctrl_txilvl_we = addr_hit[7] & reg_we & ~wr_err;
assign fifo_ctrl_txilvl_wd = reg_wdata[6:5];
assign fifo_status_txlvl_re = addr_hit[8] && reg_re;
assign fifo_status_rxlvl_re = addr_hit[8] && reg_re;
- assign ovrd_txen_we = addr_hit[9] && reg_we;
+ assign ovrd_txen_we = addr_hit[9] & reg_we & ~wr_err;
assign ovrd_txen_wd = reg_wdata[0];
- assign ovrd_txval_we = addr_hit[9] && reg_we;
+ assign ovrd_txval_we = addr_hit[9] & reg_we & ~wr_err;
assign ovrd_txval_wd = reg_wdata[1];
assign val_re = addr_hit[10] && reg_re;
- assign timeout_ctrl_val_we = addr_hit[11] && reg_we;
+ assign timeout_ctrl_val_we = addr_hit[11] & reg_we & ~wr_err;
assign timeout_ctrl_val_wd = reg_wdata[23:0];
- assign timeout_ctrl_en_we = addr_hit[11] && reg_we;
+ assign timeout_ctrl_en_we = addr_hit[11] & reg_we & ~wr_err;
assign timeout_ctrl_en_wd = reg_wdata[31];
assign usbstat_frame_re = addr_hit[12] && reg_re;
diff --git a/hw/top_earlgrey/rtl/rv_plic_reg_pkg.sv b/hw/top_earlgrey/rtl/rv_plic_reg_pkg.sv
index 4b083da..c002c46 100644
--- a/hw/top_earlgrey/rtl/rv_plic_reg_pkg.sv
+++ b/hw/top_earlgrey/rtl/rv_plic_reg_pkg.sv
@@ -782,4 +782,134 @@
parameter RV_PLIC_MSIP0_OFFSET = 9'h 110;
+ // Register Index
+ typedef enum int {
+ RV_PLIC_IP0,
+ RV_PLIC_IP1,
+ RV_PLIC_LE0,
+ RV_PLIC_LE1,
+ RV_PLIC_PRIO0,
+ RV_PLIC_PRIO1,
+ RV_PLIC_PRIO2,
+ RV_PLIC_PRIO3,
+ RV_PLIC_PRIO4,
+ RV_PLIC_PRIO5,
+ RV_PLIC_PRIO6,
+ RV_PLIC_PRIO7,
+ RV_PLIC_PRIO8,
+ RV_PLIC_PRIO9,
+ RV_PLIC_PRIO10,
+ RV_PLIC_PRIO11,
+ RV_PLIC_PRIO12,
+ RV_PLIC_PRIO13,
+ RV_PLIC_PRIO14,
+ RV_PLIC_PRIO15,
+ RV_PLIC_PRIO16,
+ RV_PLIC_PRIO17,
+ RV_PLIC_PRIO18,
+ RV_PLIC_PRIO19,
+ RV_PLIC_PRIO20,
+ RV_PLIC_PRIO21,
+ RV_PLIC_PRIO22,
+ RV_PLIC_PRIO23,
+ RV_PLIC_PRIO24,
+ RV_PLIC_PRIO25,
+ RV_PLIC_PRIO26,
+ RV_PLIC_PRIO27,
+ RV_PLIC_PRIO28,
+ RV_PLIC_PRIO29,
+ RV_PLIC_PRIO30,
+ RV_PLIC_PRIO31,
+ RV_PLIC_PRIO32,
+ RV_PLIC_PRIO33,
+ RV_PLIC_PRIO34,
+ RV_PLIC_PRIO35,
+ RV_PLIC_PRIO36,
+ RV_PLIC_PRIO37,
+ RV_PLIC_PRIO38,
+ RV_PLIC_PRIO39,
+ RV_PLIC_PRIO40,
+ RV_PLIC_PRIO41,
+ RV_PLIC_PRIO42,
+ RV_PLIC_PRIO43,
+ RV_PLIC_PRIO44,
+ RV_PLIC_PRIO45,
+ RV_PLIC_PRIO46,
+ RV_PLIC_PRIO47,
+ RV_PLIC_PRIO48,
+ RV_PLIC_PRIO49,
+ RV_PLIC_PRIO50,
+ RV_PLIC_PRIO51,
+ RV_PLIC_IE00,
+ RV_PLIC_IE01,
+ RV_PLIC_THRESHOLD0,
+ RV_PLIC_CC0,
+ RV_PLIC_MSIP0
+ } rv_plic_id_e;
+
+ // Register width information to check illegal writes
+ localparam logic [3:0] RV_PLIC_PERMIT [61] = '{
+ 4'b 1111, // index[ 0] RV_PLIC_IP0
+ 4'b 1111, // index[ 1] RV_PLIC_IP1
+ 4'b 1111, // index[ 2] RV_PLIC_LE0
+ 4'b 1111, // index[ 3] RV_PLIC_LE1
+ 4'b 0001, // index[ 4] RV_PLIC_PRIO0
+ 4'b 0001, // index[ 5] RV_PLIC_PRIO1
+ 4'b 0001, // index[ 6] RV_PLIC_PRIO2
+ 4'b 0001, // index[ 7] RV_PLIC_PRIO3
+ 4'b 0001, // index[ 8] RV_PLIC_PRIO4
+ 4'b 0001, // index[ 9] RV_PLIC_PRIO5
+ 4'b 0001, // index[10] RV_PLIC_PRIO6
+ 4'b 0001, // index[11] RV_PLIC_PRIO7
+ 4'b 0001, // index[12] RV_PLIC_PRIO8
+ 4'b 0001, // index[13] RV_PLIC_PRIO9
+ 4'b 0001, // index[14] RV_PLIC_PRIO10
+ 4'b 0001, // index[15] RV_PLIC_PRIO11
+ 4'b 0001, // index[16] RV_PLIC_PRIO12
+ 4'b 0001, // index[17] RV_PLIC_PRIO13
+ 4'b 0001, // index[18] RV_PLIC_PRIO14
+ 4'b 0001, // index[19] RV_PLIC_PRIO15
+ 4'b 0001, // index[20] RV_PLIC_PRIO16
+ 4'b 0001, // index[21] RV_PLIC_PRIO17
+ 4'b 0001, // index[22] RV_PLIC_PRIO18
+ 4'b 0001, // index[23] RV_PLIC_PRIO19
+ 4'b 0001, // index[24] RV_PLIC_PRIO20
+ 4'b 0001, // index[25] RV_PLIC_PRIO21
+ 4'b 0001, // index[26] RV_PLIC_PRIO22
+ 4'b 0001, // index[27] RV_PLIC_PRIO23
+ 4'b 0001, // index[28] RV_PLIC_PRIO24
+ 4'b 0001, // index[29] RV_PLIC_PRIO25
+ 4'b 0001, // index[30] RV_PLIC_PRIO26
+ 4'b 0001, // index[31] RV_PLIC_PRIO27
+ 4'b 0001, // index[32] RV_PLIC_PRIO28
+ 4'b 0001, // index[33] RV_PLIC_PRIO29
+ 4'b 0001, // index[34] RV_PLIC_PRIO30
+ 4'b 0001, // index[35] RV_PLIC_PRIO31
+ 4'b 0001, // index[36] RV_PLIC_PRIO32
+ 4'b 0001, // index[37] RV_PLIC_PRIO33
+ 4'b 0001, // index[38] RV_PLIC_PRIO34
+ 4'b 0001, // index[39] RV_PLIC_PRIO35
+ 4'b 0001, // index[40] RV_PLIC_PRIO36
+ 4'b 0001, // index[41] RV_PLIC_PRIO37
+ 4'b 0001, // index[42] RV_PLIC_PRIO38
+ 4'b 0001, // index[43] RV_PLIC_PRIO39
+ 4'b 0001, // index[44] RV_PLIC_PRIO40
+ 4'b 0001, // index[45] RV_PLIC_PRIO41
+ 4'b 0001, // index[46] RV_PLIC_PRIO42
+ 4'b 0001, // index[47] RV_PLIC_PRIO43
+ 4'b 0001, // index[48] RV_PLIC_PRIO44
+ 4'b 0001, // index[49] RV_PLIC_PRIO45
+ 4'b 0001, // index[50] RV_PLIC_PRIO46
+ 4'b 0001, // index[51] RV_PLIC_PRIO47
+ 4'b 0001, // index[52] RV_PLIC_PRIO48
+ 4'b 0001, // index[53] RV_PLIC_PRIO49
+ 4'b 0001, // index[54] RV_PLIC_PRIO50
+ 4'b 0001, // index[55] RV_PLIC_PRIO51
+ 4'b 1111, // index[56] RV_PLIC_IE00
+ 4'b 1111, // index[57] RV_PLIC_IE01
+ 4'b 0001, // index[58] RV_PLIC_THRESHOLD0
+ 4'b 0001, // index[59] RV_PLIC_CC0
+ 4'b 0001, // index[60] RV_PLIC_MSIP0
+ };
endpackage
+
diff --git a/hw/top_earlgrey/rtl/rv_plic_reg_top.sv b/hw/top_earlgrey/rtl/rv_plic_reg_top.sv
index ed1f9a5..ae34198 100644
--- a/hw/top_earlgrey/rtl/rv_plic_reg_top.sv
+++ b/hw/top_earlgrey/rtl/rv_plic_reg_top.sv
@@ -32,7 +32,7 @@
logic [DW-1:0] reg_rdata;
logic reg_error;
- logic malformed, addrmiss;
+ logic addrmiss, wr_err;
logic [DW-1:0] reg_rdata_next;
@@ -62,16 +62,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = malformed | addrmiss ;
-
- // Malformed request check only affects to the write access
- always_comb begin : malformed_check
- if (reg_we && (reg_be != '1)) begin
- malformed = 1'b1;
- end else begin
- malformed = 1'b0;
- end
- end
+ assign reg_error = addrmiss | wr_err;
// TODO(eunchan): Revise Register Interface logic after REG INTF finalized
// TODO(eunchan): Make concrete scenario
@@ -6118,16 +6109,16 @@
logic [60:0] addr_hit;
always_comb begin
addr_hit = '0;
- addr_hit[0] = (reg_addr == RV_PLIC_IP0_OFFSET);
- addr_hit[1] = (reg_addr == RV_PLIC_IP1_OFFSET);
- addr_hit[2] = (reg_addr == RV_PLIC_LE0_OFFSET);
- addr_hit[3] = (reg_addr == RV_PLIC_LE1_OFFSET);
- addr_hit[4] = (reg_addr == RV_PLIC_PRIO0_OFFSET);
- addr_hit[5] = (reg_addr == RV_PLIC_PRIO1_OFFSET);
- addr_hit[6] = (reg_addr == RV_PLIC_PRIO2_OFFSET);
- addr_hit[7] = (reg_addr == RV_PLIC_PRIO3_OFFSET);
- addr_hit[8] = (reg_addr == RV_PLIC_PRIO4_OFFSET);
- addr_hit[9] = (reg_addr == RV_PLIC_PRIO5_OFFSET);
+ addr_hit[ 0] = (reg_addr == RV_PLIC_IP0_OFFSET);
+ addr_hit[ 1] = (reg_addr == RV_PLIC_IP1_OFFSET);
+ addr_hit[ 2] = (reg_addr == RV_PLIC_LE0_OFFSET);
+ addr_hit[ 3] = (reg_addr == RV_PLIC_LE1_OFFSET);
+ addr_hit[ 4] = (reg_addr == RV_PLIC_PRIO0_OFFSET);
+ addr_hit[ 5] = (reg_addr == RV_PLIC_PRIO1_OFFSET);
+ addr_hit[ 6] = (reg_addr == RV_PLIC_PRIO2_OFFSET);
+ addr_hit[ 7] = (reg_addr == RV_PLIC_PRIO3_OFFSET);
+ addr_hit[ 8] = (reg_addr == RV_PLIC_PRIO4_OFFSET);
+ addr_hit[ 9] = (reg_addr == RV_PLIC_PRIO5_OFFSET);
addr_hit[10] = (reg_addr == RV_PLIC_PRIO6_OFFSET);
addr_hit[11] = (reg_addr == RV_PLIC_PRIO7_OFFSET);
addr_hit[12] = (reg_addr == RV_PLIC_PRIO8_OFFSET);
@@ -6189,7 +6180,71 @@
end
end
- // Write Enable signal
+ // Check sub-word write is permitted
+ always_comb begin
+ wr_err = 1'b0;
+ if (addr_hit[ 0] && reg_we && (RV_PLIC_PERMIT[ 0] != (RV_PLIC_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 1] && reg_we && (RV_PLIC_PERMIT[ 1] != (RV_PLIC_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 2] && reg_we && (RV_PLIC_PERMIT[ 2] != (RV_PLIC_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 3] && reg_we && (RV_PLIC_PERMIT[ 3] != (RV_PLIC_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 4] && reg_we && (RV_PLIC_PERMIT[ 4] != (RV_PLIC_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 5] && reg_we && (RV_PLIC_PERMIT[ 5] != (RV_PLIC_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 6] && reg_we && (RV_PLIC_PERMIT[ 6] != (RV_PLIC_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 7] && reg_we && (RV_PLIC_PERMIT[ 7] != (RV_PLIC_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 8] && reg_we && (RV_PLIC_PERMIT[ 8] != (RV_PLIC_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 9] && reg_we && (RV_PLIC_PERMIT[ 9] != (RV_PLIC_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[10] && reg_we && (RV_PLIC_PERMIT[10] != (RV_PLIC_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[11] && reg_we && (RV_PLIC_PERMIT[11] != (RV_PLIC_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[12] && reg_we && (RV_PLIC_PERMIT[12] != (RV_PLIC_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[13] && reg_we && (RV_PLIC_PERMIT[13] != (RV_PLIC_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[14] && reg_we && (RV_PLIC_PERMIT[14] != (RV_PLIC_PERMIT[14] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[15] && reg_we && (RV_PLIC_PERMIT[15] != (RV_PLIC_PERMIT[15] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[16] && reg_we && (RV_PLIC_PERMIT[16] != (RV_PLIC_PERMIT[16] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[17] && reg_we && (RV_PLIC_PERMIT[17] != (RV_PLIC_PERMIT[17] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[18] && reg_we && (RV_PLIC_PERMIT[18] != (RV_PLIC_PERMIT[18] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[19] && reg_we && (RV_PLIC_PERMIT[19] != (RV_PLIC_PERMIT[19] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[20] && reg_we && (RV_PLIC_PERMIT[20] != (RV_PLIC_PERMIT[20] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[21] && reg_we && (RV_PLIC_PERMIT[21] != (RV_PLIC_PERMIT[21] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[22] && reg_we && (RV_PLIC_PERMIT[22] != (RV_PLIC_PERMIT[22] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[23] && reg_we && (RV_PLIC_PERMIT[23] != (RV_PLIC_PERMIT[23] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[24] && reg_we && (RV_PLIC_PERMIT[24] != (RV_PLIC_PERMIT[24] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[25] && reg_we && (RV_PLIC_PERMIT[25] != (RV_PLIC_PERMIT[25] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[26] && reg_we && (RV_PLIC_PERMIT[26] != (RV_PLIC_PERMIT[26] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[27] && reg_we && (RV_PLIC_PERMIT[27] != (RV_PLIC_PERMIT[27] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[28] && reg_we && (RV_PLIC_PERMIT[28] != (RV_PLIC_PERMIT[28] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[29] && reg_we && (RV_PLIC_PERMIT[29] != (RV_PLIC_PERMIT[29] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[30] && reg_we && (RV_PLIC_PERMIT[30] != (RV_PLIC_PERMIT[30] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[31] && reg_we && (RV_PLIC_PERMIT[31] != (RV_PLIC_PERMIT[31] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[32] && reg_we && (RV_PLIC_PERMIT[32] != (RV_PLIC_PERMIT[32] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[33] && reg_we && (RV_PLIC_PERMIT[33] != (RV_PLIC_PERMIT[33] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[34] && reg_we && (RV_PLIC_PERMIT[34] != (RV_PLIC_PERMIT[34] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[35] && reg_we && (RV_PLIC_PERMIT[35] != (RV_PLIC_PERMIT[35] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[36] && reg_we && (RV_PLIC_PERMIT[36] != (RV_PLIC_PERMIT[36] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[37] && reg_we && (RV_PLIC_PERMIT[37] != (RV_PLIC_PERMIT[37] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[38] && reg_we && (RV_PLIC_PERMIT[38] != (RV_PLIC_PERMIT[38] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[39] && reg_we && (RV_PLIC_PERMIT[39] != (RV_PLIC_PERMIT[39] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[40] && reg_we && (RV_PLIC_PERMIT[40] != (RV_PLIC_PERMIT[40] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[41] && reg_we && (RV_PLIC_PERMIT[41] != (RV_PLIC_PERMIT[41] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[42] && reg_we && (RV_PLIC_PERMIT[42] != (RV_PLIC_PERMIT[42] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[43] && reg_we && (RV_PLIC_PERMIT[43] != (RV_PLIC_PERMIT[43] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[44] && reg_we && (RV_PLIC_PERMIT[44] != (RV_PLIC_PERMIT[44] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[45] && reg_we && (RV_PLIC_PERMIT[45] != (RV_PLIC_PERMIT[45] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[46] && reg_we && (RV_PLIC_PERMIT[46] != (RV_PLIC_PERMIT[46] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[47] && reg_we && (RV_PLIC_PERMIT[47] != (RV_PLIC_PERMIT[47] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[48] && reg_we && (RV_PLIC_PERMIT[48] != (RV_PLIC_PERMIT[48] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[49] && reg_we && (RV_PLIC_PERMIT[49] != (RV_PLIC_PERMIT[49] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[50] && reg_we && (RV_PLIC_PERMIT[50] != (RV_PLIC_PERMIT[50] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[51] && reg_we && (RV_PLIC_PERMIT[51] != (RV_PLIC_PERMIT[51] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[52] && reg_we && (RV_PLIC_PERMIT[52] != (RV_PLIC_PERMIT[52] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[53] && reg_we && (RV_PLIC_PERMIT[53] != (RV_PLIC_PERMIT[53] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[54] && reg_we && (RV_PLIC_PERMIT[54] != (RV_PLIC_PERMIT[54] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[55] && reg_we && (RV_PLIC_PERMIT[55] != (RV_PLIC_PERMIT[55] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[56] && reg_we && (RV_PLIC_PERMIT[56] != (RV_PLIC_PERMIT[56] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[57] && reg_we && (RV_PLIC_PERMIT[57] != (RV_PLIC_PERMIT[57] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[58] && reg_we && (RV_PLIC_PERMIT[58] != (RV_PLIC_PERMIT[58] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[59] && reg_we && (RV_PLIC_PERMIT[59] != (RV_PLIC_PERMIT[59] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[60] && reg_we && (RV_PLIC_PERMIT[60] != (RV_PLIC_PERMIT[60] & reg_be))) wr_err = 1'b1 ;
+ end
@@ -6243,482 +6298,482 @@
- assign le0_le0_we = addr_hit[2] && reg_we;
+ assign le0_le0_we = addr_hit[2] & reg_we & ~wr_err;
assign le0_le0_wd = reg_wdata[0];
- assign le0_le1_we = addr_hit[2] && reg_we;
+ assign le0_le1_we = addr_hit[2] & reg_we & ~wr_err;
assign le0_le1_wd = reg_wdata[1];
- assign le0_le2_we = addr_hit[2] && reg_we;
+ assign le0_le2_we = addr_hit[2] & reg_we & ~wr_err;
assign le0_le2_wd = reg_wdata[2];
- assign le0_le3_we = addr_hit[2] && reg_we;
+ assign le0_le3_we = addr_hit[2] & reg_we & ~wr_err;
assign le0_le3_wd = reg_wdata[3];
- assign le0_le4_we = addr_hit[2] && reg_we;
+ assign le0_le4_we = addr_hit[2] & reg_we & ~wr_err;
assign le0_le4_wd = reg_wdata[4];
- assign le0_le5_we = addr_hit[2] && reg_we;
+ assign le0_le5_we = addr_hit[2] & reg_we & ~wr_err;
assign le0_le5_wd = reg_wdata[5];
- assign le0_le6_we = addr_hit[2] && reg_we;
+ assign le0_le6_we = addr_hit[2] & reg_we & ~wr_err;
assign le0_le6_wd = reg_wdata[6];
- assign le0_le7_we = addr_hit[2] && reg_we;
+ assign le0_le7_we = addr_hit[2] & reg_we & ~wr_err;
assign le0_le7_wd = reg_wdata[7];
- assign le0_le8_we = addr_hit[2] && reg_we;
+ assign le0_le8_we = addr_hit[2] & reg_we & ~wr_err;
assign le0_le8_wd = reg_wdata[8];
- assign le0_le9_we = addr_hit[2] && reg_we;
+ assign le0_le9_we = addr_hit[2] & reg_we & ~wr_err;
assign le0_le9_wd = reg_wdata[9];
- assign le0_le10_we = addr_hit[2] && reg_we;
+ assign le0_le10_we = addr_hit[2] & reg_we & ~wr_err;
assign le0_le10_wd = reg_wdata[10];
- assign le0_le11_we = addr_hit[2] && reg_we;
+ assign le0_le11_we = addr_hit[2] & reg_we & ~wr_err;
assign le0_le11_wd = reg_wdata[11];
- assign le0_le12_we = addr_hit[2] && reg_we;
+ assign le0_le12_we = addr_hit[2] & reg_we & ~wr_err;
assign le0_le12_wd = reg_wdata[12];
- assign le0_le13_we = addr_hit[2] && reg_we;
+ assign le0_le13_we = addr_hit[2] & reg_we & ~wr_err;
assign le0_le13_wd = reg_wdata[13];
- assign le0_le14_we = addr_hit[2] && reg_we;
+ assign le0_le14_we = addr_hit[2] & reg_we & ~wr_err;
assign le0_le14_wd = reg_wdata[14];
- assign le0_le15_we = addr_hit[2] && reg_we;
+ assign le0_le15_we = addr_hit[2] & reg_we & ~wr_err;
assign le0_le15_wd = reg_wdata[15];
- assign le0_le16_we = addr_hit[2] && reg_we;
+ assign le0_le16_we = addr_hit[2] & reg_we & ~wr_err;
assign le0_le16_wd = reg_wdata[16];
- assign le0_le17_we = addr_hit[2] && reg_we;
+ assign le0_le17_we = addr_hit[2] & reg_we & ~wr_err;
assign le0_le17_wd = reg_wdata[17];
- assign le0_le18_we = addr_hit[2] && reg_we;
+ assign le0_le18_we = addr_hit[2] & reg_we & ~wr_err;
assign le0_le18_wd = reg_wdata[18];
- assign le0_le19_we = addr_hit[2] && reg_we;
+ assign le0_le19_we = addr_hit[2] & reg_we & ~wr_err;
assign le0_le19_wd = reg_wdata[19];
- assign le0_le20_we = addr_hit[2] && reg_we;
+ assign le0_le20_we = addr_hit[2] & reg_we & ~wr_err;
assign le0_le20_wd = reg_wdata[20];
- assign le0_le21_we = addr_hit[2] && reg_we;
+ assign le0_le21_we = addr_hit[2] & reg_we & ~wr_err;
assign le0_le21_wd = reg_wdata[21];
- assign le0_le22_we = addr_hit[2] && reg_we;
+ assign le0_le22_we = addr_hit[2] & reg_we & ~wr_err;
assign le0_le22_wd = reg_wdata[22];
- assign le0_le23_we = addr_hit[2] && reg_we;
+ assign le0_le23_we = addr_hit[2] & reg_we & ~wr_err;
assign le0_le23_wd = reg_wdata[23];
- assign le0_le24_we = addr_hit[2] && reg_we;
+ assign le0_le24_we = addr_hit[2] & reg_we & ~wr_err;
assign le0_le24_wd = reg_wdata[24];
- assign le0_le25_we = addr_hit[2] && reg_we;
+ assign le0_le25_we = addr_hit[2] & reg_we & ~wr_err;
assign le0_le25_wd = reg_wdata[25];
- assign le0_le26_we = addr_hit[2] && reg_we;
+ assign le0_le26_we = addr_hit[2] & reg_we & ~wr_err;
assign le0_le26_wd = reg_wdata[26];
- assign le0_le27_we = addr_hit[2] && reg_we;
+ assign le0_le27_we = addr_hit[2] & reg_we & ~wr_err;
assign le0_le27_wd = reg_wdata[27];
- assign le0_le28_we = addr_hit[2] && reg_we;
+ assign le0_le28_we = addr_hit[2] & reg_we & ~wr_err;
assign le0_le28_wd = reg_wdata[28];
- assign le0_le29_we = addr_hit[2] && reg_we;
+ assign le0_le29_we = addr_hit[2] & reg_we & ~wr_err;
assign le0_le29_wd = reg_wdata[29];
- assign le0_le30_we = addr_hit[2] && reg_we;
+ assign le0_le30_we = addr_hit[2] & reg_we & ~wr_err;
assign le0_le30_wd = reg_wdata[30];
- assign le0_le31_we = addr_hit[2] && reg_we;
+ assign le0_le31_we = addr_hit[2] & reg_we & ~wr_err;
assign le0_le31_wd = reg_wdata[31];
- assign le1_le32_we = addr_hit[3] && reg_we;
+ assign le1_le32_we = addr_hit[3] & reg_we & ~wr_err;
assign le1_le32_wd = reg_wdata[0];
- assign le1_le33_we = addr_hit[3] && reg_we;
+ assign le1_le33_we = addr_hit[3] & reg_we & ~wr_err;
assign le1_le33_wd = reg_wdata[1];
- assign le1_le34_we = addr_hit[3] && reg_we;
+ assign le1_le34_we = addr_hit[3] & reg_we & ~wr_err;
assign le1_le34_wd = reg_wdata[2];
- assign le1_le35_we = addr_hit[3] && reg_we;
+ assign le1_le35_we = addr_hit[3] & reg_we & ~wr_err;
assign le1_le35_wd = reg_wdata[3];
- assign le1_le36_we = addr_hit[3] && reg_we;
+ assign le1_le36_we = addr_hit[3] & reg_we & ~wr_err;
assign le1_le36_wd = reg_wdata[4];
- assign le1_le37_we = addr_hit[3] && reg_we;
+ assign le1_le37_we = addr_hit[3] & reg_we & ~wr_err;
assign le1_le37_wd = reg_wdata[5];
- assign le1_le38_we = addr_hit[3] && reg_we;
+ assign le1_le38_we = addr_hit[3] & reg_we & ~wr_err;
assign le1_le38_wd = reg_wdata[6];
- assign le1_le39_we = addr_hit[3] && reg_we;
+ assign le1_le39_we = addr_hit[3] & reg_we & ~wr_err;
assign le1_le39_wd = reg_wdata[7];
- assign le1_le40_we = addr_hit[3] && reg_we;
+ assign le1_le40_we = addr_hit[3] & reg_we & ~wr_err;
assign le1_le40_wd = reg_wdata[8];
- assign le1_le41_we = addr_hit[3] && reg_we;
+ assign le1_le41_we = addr_hit[3] & reg_we & ~wr_err;
assign le1_le41_wd = reg_wdata[9];
- assign le1_le42_we = addr_hit[3] && reg_we;
+ assign le1_le42_we = addr_hit[3] & reg_we & ~wr_err;
assign le1_le42_wd = reg_wdata[10];
- assign le1_le43_we = addr_hit[3] && reg_we;
+ assign le1_le43_we = addr_hit[3] & reg_we & ~wr_err;
assign le1_le43_wd = reg_wdata[11];
- assign le1_le44_we = addr_hit[3] && reg_we;
+ assign le1_le44_we = addr_hit[3] & reg_we & ~wr_err;
assign le1_le44_wd = reg_wdata[12];
- assign le1_le45_we = addr_hit[3] && reg_we;
+ assign le1_le45_we = addr_hit[3] & reg_we & ~wr_err;
assign le1_le45_wd = reg_wdata[13];
- assign le1_le46_we = addr_hit[3] && reg_we;
+ assign le1_le46_we = addr_hit[3] & reg_we & ~wr_err;
assign le1_le46_wd = reg_wdata[14];
- assign le1_le47_we = addr_hit[3] && reg_we;
+ assign le1_le47_we = addr_hit[3] & reg_we & ~wr_err;
assign le1_le47_wd = reg_wdata[15];
- assign le1_le48_we = addr_hit[3] && reg_we;
+ assign le1_le48_we = addr_hit[3] & reg_we & ~wr_err;
assign le1_le48_wd = reg_wdata[16];
- assign le1_le49_we = addr_hit[3] && reg_we;
+ assign le1_le49_we = addr_hit[3] & reg_we & ~wr_err;
assign le1_le49_wd = reg_wdata[17];
- assign le1_le50_we = addr_hit[3] && reg_we;
+ assign le1_le50_we = addr_hit[3] & reg_we & ~wr_err;
assign le1_le50_wd = reg_wdata[18];
- assign le1_le51_we = addr_hit[3] && reg_we;
+ assign le1_le51_we = addr_hit[3] & reg_we & ~wr_err;
assign le1_le51_wd = reg_wdata[19];
- assign prio0_we = addr_hit[4] && reg_we;
+ assign prio0_we = addr_hit[4] & reg_we & ~wr_err;
assign prio0_wd = reg_wdata[1:0];
- assign prio1_we = addr_hit[5] && reg_we;
+ assign prio1_we = addr_hit[5] & reg_we & ~wr_err;
assign prio1_wd = reg_wdata[1:0];
- assign prio2_we = addr_hit[6] && reg_we;
+ assign prio2_we = addr_hit[6] & reg_we & ~wr_err;
assign prio2_wd = reg_wdata[1:0];
- assign prio3_we = addr_hit[7] && reg_we;
+ assign prio3_we = addr_hit[7] & reg_we & ~wr_err;
assign prio3_wd = reg_wdata[1:0];
- assign prio4_we = addr_hit[8] && reg_we;
+ assign prio4_we = addr_hit[8] & reg_we & ~wr_err;
assign prio4_wd = reg_wdata[1:0];
- assign prio5_we = addr_hit[9] && reg_we;
+ assign prio5_we = addr_hit[9] & reg_we & ~wr_err;
assign prio5_wd = reg_wdata[1:0];
- assign prio6_we = addr_hit[10] && reg_we;
+ assign prio6_we = addr_hit[10] & reg_we & ~wr_err;
assign prio6_wd = reg_wdata[1:0];
- assign prio7_we = addr_hit[11] && reg_we;
+ assign prio7_we = addr_hit[11] & reg_we & ~wr_err;
assign prio7_wd = reg_wdata[1:0];
- assign prio8_we = addr_hit[12] && reg_we;
+ assign prio8_we = addr_hit[12] & reg_we & ~wr_err;
assign prio8_wd = reg_wdata[1:0];
- assign prio9_we = addr_hit[13] && reg_we;
+ assign prio9_we = addr_hit[13] & reg_we & ~wr_err;
assign prio9_wd = reg_wdata[1:0];
- assign prio10_we = addr_hit[14] && reg_we;
+ assign prio10_we = addr_hit[14] & reg_we & ~wr_err;
assign prio10_wd = reg_wdata[1:0];
- assign prio11_we = addr_hit[15] && reg_we;
+ assign prio11_we = addr_hit[15] & reg_we & ~wr_err;
assign prio11_wd = reg_wdata[1:0];
- assign prio12_we = addr_hit[16] && reg_we;
+ assign prio12_we = addr_hit[16] & reg_we & ~wr_err;
assign prio12_wd = reg_wdata[1:0];
- assign prio13_we = addr_hit[17] && reg_we;
+ assign prio13_we = addr_hit[17] & reg_we & ~wr_err;
assign prio13_wd = reg_wdata[1:0];
- assign prio14_we = addr_hit[18] && reg_we;
+ assign prio14_we = addr_hit[18] & reg_we & ~wr_err;
assign prio14_wd = reg_wdata[1:0];
- assign prio15_we = addr_hit[19] && reg_we;
+ assign prio15_we = addr_hit[19] & reg_we & ~wr_err;
assign prio15_wd = reg_wdata[1:0];
- assign prio16_we = addr_hit[20] && reg_we;
+ assign prio16_we = addr_hit[20] & reg_we & ~wr_err;
assign prio16_wd = reg_wdata[1:0];
- assign prio17_we = addr_hit[21] && reg_we;
+ assign prio17_we = addr_hit[21] & reg_we & ~wr_err;
assign prio17_wd = reg_wdata[1:0];
- assign prio18_we = addr_hit[22] && reg_we;
+ assign prio18_we = addr_hit[22] & reg_we & ~wr_err;
assign prio18_wd = reg_wdata[1:0];
- assign prio19_we = addr_hit[23] && reg_we;
+ assign prio19_we = addr_hit[23] & reg_we & ~wr_err;
assign prio19_wd = reg_wdata[1:0];
- assign prio20_we = addr_hit[24] && reg_we;
+ assign prio20_we = addr_hit[24] & reg_we & ~wr_err;
assign prio20_wd = reg_wdata[1:0];
- assign prio21_we = addr_hit[25] && reg_we;
+ assign prio21_we = addr_hit[25] & reg_we & ~wr_err;
assign prio21_wd = reg_wdata[1:0];
- assign prio22_we = addr_hit[26] && reg_we;
+ assign prio22_we = addr_hit[26] & reg_we & ~wr_err;
assign prio22_wd = reg_wdata[1:0];
- assign prio23_we = addr_hit[27] && reg_we;
+ assign prio23_we = addr_hit[27] & reg_we & ~wr_err;
assign prio23_wd = reg_wdata[1:0];
- assign prio24_we = addr_hit[28] && reg_we;
+ assign prio24_we = addr_hit[28] & reg_we & ~wr_err;
assign prio24_wd = reg_wdata[1:0];
- assign prio25_we = addr_hit[29] && reg_we;
+ assign prio25_we = addr_hit[29] & reg_we & ~wr_err;
assign prio25_wd = reg_wdata[1:0];
- assign prio26_we = addr_hit[30] && reg_we;
+ assign prio26_we = addr_hit[30] & reg_we & ~wr_err;
assign prio26_wd = reg_wdata[1:0];
- assign prio27_we = addr_hit[31] && reg_we;
+ assign prio27_we = addr_hit[31] & reg_we & ~wr_err;
assign prio27_wd = reg_wdata[1:0];
- assign prio28_we = addr_hit[32] && reg_we;
+ assign prio28_we = addr_hit[32] & reg_we & ~wr_err;
assign prio28_wd = reg_wdata[1:0];
- assign prio29_we = addr_hit[33] && reg_we;
+ assign prio29_we = addr_hit[33] & reg_we & ~wr_err;
assign prio29_wd = reg_wdata[1:0];
- assign prio30_we = addr_hit[34] && reg_we;
+ assign prio30_we = addr_hit[34] & reg_we & ~wr_err;
assign prio30_wd = reg_wdata[1:0];
- assign prio31_we = addr_hit[35] && reg_we;
+ assign prio31_we = addr_hit[35] & reg_we & ~wr_err;
assign prio31_wd = reg_wdata[1:0];
- assign prio32_we = addr_hit[36] && reg_we;
+ assign prio32_we = addr_hit[36] & reg_we & ~wr_err;
assign prio32_wd = reg_wdata[1:0];
- assign prio33_we = addr_hit[37] && reg_we;
+ assign prio33_we = addr_hit[37] & reg_we & ~wr_err;
assign prio33_wd = reg_wdata[1:0];
- assign prio34_we = addr_hit[38] && reg_we;
+ assign prio34_we = addr_hit[38] & reg_we & ~wr_err;
assign prio34_wd = reg_wdata[1:0];
- assign prio35_we = addr_hit[39] && reg_we;
+ assign prio35_we = addr_hit[39] & reg_we & ~wr_err;
assign prio35_wd = reg_wdata[1:0];
- assign prio36_we = addr_hit[40] && reg_we;
+ assign prio36_we = addr_hit[40] & reg_we & ~wr_err;
assign prio36_wd = reg_wdata[1:0];
- assign prio37_we = addr_hit[41] && reg_we;
+ assign prio37_we = addr_hit[41] & reg_we & ~wr_err;
assign prio37_wd = reg_wdata[1:0];
- assign prio38_we = addr_hit[42] && reg_we;
+ assign prio38_we = addr_hit[42] & reg_we & ~wr_err;
assign prio38_wd = reg_wdata[1:0];
- assign prio39_we = addr_hit[43] && reg_we;
+ assign prio39_we = addr_hit[43] & reg_we & ~wr_err;
assign prio39_wd = reg_wdata[1:0];
- assign prio40_we = addr_hit[44] && reg_we;
+ assign prio40_we = addr_hit[44] & reg_we & ~wr_err;
assign prio40_wd = reg_wdata[1:0];
- assign prio41_we = addr_hit[45] && reg_we;
+ assign prio41_we = addr_hit[45] & reg_we & ~wr_err;
assign prio41_wd = reg_wdata[1:0];
- assign prio42_we = addr_hit[46] && reg_we;
+ assign prio42_we = addr_hit[46] & reg_we & ~wr_err;
assign prio42_wd = reg_wdata[1:0];
- assign prio43_we = addr_hit[47] && reg_we;
+ assign prio43_we = addr_hit[47] & reg_we & ~wr_err;
assign prio43_wd = reg_wdata[1:0];
- assign prio44_we = addr_hit[48] && reg_we;
+ assign prio44_we = addr_hit[48] & reg_we & ~wr_err;
assign prio44_wd = reg_wdata[1:0];
- assign prio45_we = addr_hit[49] && reg_we;
+ assign prio45_we = addr_hit[49] & reg_we & ~wr_err;
assign prio45_wd = reg_wdata[1:0];
- assign prio46_we = addr_hit[50] && reg_we;
+ assign prio46_we = addr_hit[50] & reg_we & ~wr_err;
assign prio46_wd = reg_wdata[1:0];
- assign prio47_we = addr_hit[51] && reg_we;
+ assign prio47_we = addr_hit[51] & reg_we & ~wr_err;
assign prio47_wd = reg_wdata[1:0];
- assign prio48_we = addr_hit[52] && reg_we;
+ assign prio48_we = addr_hit[52] & reg_we & ~wr_err;
assign prio48_wd = reg_wdata[1:0];
- assign prio49_we = addr_hit[53] && reg_we;
+ assign prio49_we = addr_hit[53] & reg_we & ~wr_err;
assign prio49_wd = reg_wdata[1:0];
- assign prio50_we = addr_hit[54] && reg_we;
+ assign prio50_we = addr_hit[54] & reg_we & ~wr_err;
assign prio50_wd = reg_wdata[1:0];
- assign prio51_we = addr_hit[55] && reg_we;
+ assign prio51_we = addr_hit[55] & reg_we & ~wr_err;
assign prio51_wd = reg_wdata[1:0];
- assign ie00_e0_we = addr_hit[56] && reg_we;
+ assign ie00_e0_we = addr_hit[56] & reg_we & ~wr_err;
assign ie00_e0_wd = reg_wdata[0];
- assign ie00_e1_we = addr_hit[56] && reg_we;
+ assign ie00_e1_we = addr_hit[56] & reg_we & ~wr_err;
assign ie00_e1_wd = reg_wdata[1];
- assign ie00_e2_we = addr_hit[56] && reg_we;
+ assign ie00_e2_we = addr_hit[56] & reg_we & ~wr_err;
assign ie00_e2_wd = reg_wdata[2];
- assign ie00_e3_we = addr_hit[56] && reg_we;
+ assign ie00_e3_we = addr_hit[56] & reg_we & ~wr_err;
assign ie00_e3_wd = reg_wdata[3];
- assign ie00_e4_we = addr_hit[56] && reg_we;
+ assign ie00_e4_we = addr_hit[56] & reg_we & ~wr_err;
assign ie00_e4_wd = reg_wdata[4];
- assign ie00_e5_we = addr_hit[56] && reg_we;
+ assign ie00_e5_we = addr_hit[56] & reg_we & ~wr_err;
assign ie00_e5_wd = reg_wdata[5];
- assign ie00_e6_we = addr_hit[56] && reg_we;
+ assign ie00_e6_we = addr_hit[56] & reg_we & ~wr_err;
assign ie00_e6_wd = reg_wdata[6];
- assign ie00_e7_we = addr_hit[56] && reg_we;
+ assign ie00_e7_we = addr_hit[56] & reg_we & ~wr_err;
assign ie00_e7_wd = reg_wdata[7];
- assign ie00_e8_we = addr_hit[56] && reg_we;
+ assign ie00_e8_we = addr_hit[56] & reg_we & ~wr_err;
assign ie00_e8_wd = reg_wdata[8];
- assign ie00_e9_we = addr_hit[56] && reg_we;
+ assign ie00_e9_we = addr_hit[56] & reg_we & ~wr_err;
assign ie00_e9_wd = reg_wdata[9];
- assign ie00_e10_we = addr_hit[56] && reg_we;
+ assign ie00_e10_we = addr_hit[56] & reg_we & ~wr_err;
assign ie00_e10_wd = reg_wdata[10];
- assign ie00_e11_we = addr_hit[56] && reg_we;
+ assign ie00_e11_we = addr_hit[56] & reg_we & ~wr_err;
assign ie00_e11_wd = reg_wdata[11];
- assign ie00_e12_we = addr_hit[56] && reg_we;
+ assign ie00_e12_we = addr_hit[56] & reg_we & ~wr_err;
assign ie00_e12_wd = reg_wdata[12];
- assign ie00_e13_we = addr_hit[56] && reg_we;
+ assign ie00_e13_we = addr_hit[56] & reg_we & ~wr_err;
assign ie00_e13_wd = reg_wdata[13];
- assign ie00_e14_we = addr_hit[56] && reg_we;
+ assign ie00_e14_we = addr_hit[56] & reg_we & ~wr_err;
assign ie00_e14_wd = reg_wdata[14];
- assign ie00_e15_we = addr_hit[56] && reg_we;
+ assign ie00_e15_we = addr_hit[56] & reg_we & ~wr_err;
assign ie00_e15_wd = reg_wdata[15];
- assign ie00_e16_we = addr_hit[56] && reg_we;
+ assign ie00_e16_we = addr_hit[56] & reg_we & ~wr_err;
assign ie00_e16_wd = reg_wdata[16];
- assign ie00_e17_we = addr_hit[56] && reg_we;
+ assign ie00_e17_we = addr_hit[56] & reg_we & ~wr_err;
assign ie00_e17_wd = reg_wdata[17];
- assign ie00_e18_we = addr_hit[56] && reg_we;
+ assign ie00_e18_we = addr_hit[56] & reg_we & ~wr_err;
assign ie00_e18_wd = reg_wdata[18];
- assign ie00_e19_we = addr_hit[56] && reg_we;
+ assign ie00_e19_we = addr_hit[56] & reg_we & ~wr_err;
assign ie00_e19_wd = reg_wdata[19];
- assign ie00_e20_we = addr_hit[56] && reg_we;
+ assign ie00_e20_we = addr_hit[56] & reg_we & ~wr_err;
assign ie00_e20_wd = reg_wdata[20];
- assign ie00_e21_we = addr_hit[56] && reg_we;
+ assign ie00_e21_we = addr_hit[56] & reg_we & ~wr_err;
assign ie00_e21_wd = reg_wdata[21];
- assign ie00_e22_we = addr_hit[56] && reg_we;
+ assign ie00_e22_we = addr_hit[56] & reg_we & ~wr_err;
assign ie00_e22_wd = reg_wdata[22];
- assign ie00_e23_we = addr_hit[56] && reg_we;
+ assign ie00_e23_we = addr_hit[56] & reg_we & ~wr_err;
assign ie00_e23_wd = reg_wdata[23];
- assign ie00_e24_we = addr_hit[56] && reg_we;
+ assign ie00_e24_we = addr_hit[56] & reg_we & ~wr_err;
assign ie00_e24_wd = reg_wdata[24];
- assign ie00_e25_we = addr_hit[56] && reg_we;
+ assign ie00_e25_we = addr_hit[56] & reg_we & ~wr_err;
assign ie00_e25_wd = reg_wdata[25];
- assign ie00_e26_we = addr_hit[56] && reg_we;
+ assign ie00_e26_we = addr_hit[56] & reg_we & ~wr_err;
assign ie00_e26_wd = reg_wdata[26];
- assign ie00_e27_we = addr_hit[56] && reg_we;
+ assign ie00_e27_we = addr_hit[56] & reg_we & ~wr_err;
assign ie00_e27_wd = reg_wdata[27];
- assign ie00_e28_we = addr_hit[56] && reg_we;
+ assign ie00_e28_we = addr_hit[56] & reg_we & ~wr_err;
assign ie00_e28_wd = reg_wdata[28];
- assign ie00_e29_we = addr_hit[56] && reg_we;
+ assign ie00_e29_we = addr_hit[56] & reg_we & ~wr_err;
assign ie00_e29_wd = reg_wdata[29];
- assign ie00_e30_we = addr_hit[56] && reg_we;
+ assign ie00_e30_we = addr_hit[56] & reg_we & ~wr_err;
assign ie00_e30_wd = reg_wdata[30];
- assign ie00_e31_we = addr_hit[56] && reg_we;
+ assign ie00_e31_we = addr_hit[56] & reg_we & ~wr_err;
assign ie00_e31_wd = reg_wdata[31];
- assign ie01_e32_we = addr_hit[57] && reg_we;
+ assign ie01_e32_we = addr_hit[57] & reg_we & ~wr_err;
assign ie01_e32_wd = reg_wdata[0];
- assign ie01_e33_we = addr_hit[57] && reg_we;
+ assign ie01_e33_we = addr_hit[57] & reg_we & ~wr_err;
assign ie01_e33_wd = reg_wdata[1];
- assign ie01_e34_we = addr_hit[57] && reg_we;
+ assign ie01_e34_we = addr_hit[57] & reg_we & ~wr_err;
assign ie01_e34_wd = reg_wdata[2];
- assign ie01_e35_we = addr_hit[57] && reg_we;
+ assign ie01_e35_we = addr_hit[57] & reg_we & ~wr_err;
assign ie01_e35_wd = reg_wdata[3];
- assign ie01_e36_we = addr_hit[57] && reg_we;
+ assign ie01_e36_we = addr_hit[57] & reg_we & ~wr_err;
assign ie01_e36_wd = reg_wdata[4];
- assign ie01_e37_we = addr_hit[57] && reg_we;
+ assign ie01_e37_we = addr_hit[57] & reg_we & ~wr_err;
assign ie01_e37_wd = reg_wdata[5];
- assign ie01_e38_we = addr_hit[57] && reg_we;
+ assign ie01_e38_we = addr_hit[57] & reg_we & ~wr_err;
assign ie01_e38_wd = reg_wdata[6];
- assign ie01_e39_we = addr_hit[57] && reg_we;
+ assign ie01_e39_we = addr_hit[57] & reg_we & ~wr_err;
assign ie01_e39_wd = reg_wdata[7];
- assign ie01_e40_we = addr_hit[57] && reg_we;
+ assign ie01_e40_we = addr_hit[57] & reg_we & ~wr_err;
assign ie01_e40_wd = reg_wdata[8];
- assign ie01_e41_we = addr_hit[57] && reg_we;
+ assign ie01_e41_we = addr_hit[57] & reg_we & ~wr_err;
assign ie01_e41_wd = reg_wdata[9];
- assign ie01_e42_we = addr_hit[57] && reg_we;
+ assign ie01_e42_we = addr_hit[57] & reg_we & ~wr_err;
assign ie01_e42_wd = reg_wdata[10];
- assign ie01_e43_we = addr_hit[57] && reg_we;
+ assign ie01_e43_we = addr_hit[57] & reg_we & ~wr_err;
assign ie01_e43_wd = reg_wdata[11];
- assign ie01_e44_we = addr_hit[57] && reg_we;
+ assign ie01_e44_we = addr_hit[57] & reg_we & ~wr_err;
assign ie01_e44_wd = reg_wdata[12];
- assign ie01_e45_we = addr_hit[57] && reg_we;
+ assign ie01_e45_we = addr_hit[57] & reg_we & ~wr_err;
assign ie01_e45_wd = reg_wdata[13];
- assign ie01_e46_we = addr_hit[57] && reg_we;
+ assign ie01_e46_we = addr_hit[57] & reg_we & ~wr_err;
assign ie01_e46_wd = reg_wdata[14];
- assign ie01_e47_we = addr_hit[57] && reg_we;
+ assign ie01_e47_we = addr_hit[57] & reg_we & ~wr_err;
assign ie01_e47_wd = reg_wdata[15];
- assign ie01_e48_we = addr_hit[57] && reg_we;
+ assign ie01_e48_we = addr_hit[57] & reg_we & ~wr_err;
assign ie01_e48_wd = reg_wdata[16];
- assign ie01_e49_we = addr_hit[57] && reg_we;
+ assign ie01_e49_we = addr_hit[57] & reg_we & ~wr_err;
assign ie01_e49_wd = reg_wdata[17];
- assign ie01_e50_we = addr_hit[57] && reg_we;
+ assign ie01_e50_we = addr_hit[57] & reg_we & ~wr_err;
assign ie01_e50_wd = reg_wdata[18];
- assign ie01_e51_we = addr_hit[57] && reg_we;
+ assign ie01_e51_we = addr_hit[57] & reg_we & ~wr_err;
assign ie01_e51_wd = reg_wdata[19];
- assign threshold0_we = addr_hit[58] && reg_we;
+ assign threshold0_we = addr_hit[58] & reg_we & ~wr_err;
assign threshold0_wd = reg_wdata[1:0];
- assign cc0_we = addr_hit[59] && reg_we;
+ assign cc0_we = addr_hit[59] & reg_we & ~wr_err;
assign cc0_wd = reg_wdata[5:0];
assign cc0_re = addr_hit[59] && reg_re;
- assign msip0_we = addr_hit[60] && reg_we;
+ assign msip0_we = addr_hit[60] & reg_we & ~wr_err;
assign msip0_wd = reg_wdata[0];
// Read data return
diff --git a/util/reggen/gen_rtl.py b/util/reggen/gen_rtl.py
index c7d4bfa..9e2ce58 100644
--- a/util/reggen/gen_rtl.py
+++ b/util/reggen/gen_rtl.py
@@ -55,6 +55,7 @@
dvrights = "RO" # Used by UVM REG only
regwen = ""
fields = []
+ width = 0 # indicate register size
def __init__(self):
self.name = ""
@@ -66,6 +67,7 @@
self.dvrights = "RO" # Used by UVM REG only
self.regwen = ""
self.fields = []
+ self.width = 0
class Window():
@@ -78,6 +80,7 @@
self.limit_addr = 0
self.n_bits = 0
+
class Block():
width = 32
addr_width = 12
@@ -96,6 +99,7 @@
self.wins = []
self.blocks = []
+
def escape_name(name):
return name.lower().replace(' ', '_')
@@ -156,6 +160,7 @@
field = parse_field(f, reg, len(obj["fields"]))
if field != None:
reg.fields.append(field)
+ reg.width = max(reg.width, field.msb + 1)
# TODO(eunchan): Field bitfield overlapping check
log.info("R[0x%04x]: %s ", reg.offset, reg.name)
diff --git a/util/reggen/reg_pkg.tpl.sv b/util/reggen/reg_pkg.tpl.sv
index 0c43c4e..b2f2223 100644
--- a/util/reggen/reg_pkg.tpl.sv
+++ b/util/reggen/reg_pkg.tpl.sv
@@ -4,6 +4,10 @@
//
// Register Package auto-generated by `reggen` containing data structure
+<%
+ num_regs = len(block.regs)
+ max_regs_char = len("{}".format(num_regs-1))
+%>\
package ${block.name}_reg_pkg;
// Register to internal design logic
@@ -135,13 +139,25 @@
parameter ${block.name.upper()}_${w.name.upper()}_SIZE = ${block.addr_width}'h ${"%x" % (w.limit_addr - w.base_addr)};
% endfor
-## typedef enum int {
-## % for r in block.regs:
-## % if loop.last:
-## ${block.name.upper()}_${r.name.upper()}
-## % else:
-## ${block.name.upper()}_${r.name.upper()},
-## % endif
-## % endfor
-## } ${block.name}_reg_e;
+ // Register Index
+ typedef enum int {
+% for r in block.regs:
+ ${block.name.upper()}_${r.name.upper()}${"" if loop.last else ","}
+% endfor
+ } ${block.name}_id_e;
+
+ // Register width information to check illegal writes
+ localparam logic [3:0] ${block.name.upper()}_PERMIT [${len(block.regs)}] = '{
+% for i,r in enumerate(block.regs):
+<% index_str = "{}".format(i).rjust(max_regs_char) %>\
+ % if r.width > 16:
+ 4'b 1111${" " if i == max_regs else ","} // index[${index_str}] ${block.name.upper()}_${r.name.upper()}
+ % elif r.width > 8:
+ 4'b 0011${" " if i == max_regs else ","} // index[${index_str}] ${block.name.upper()}_${r.name.upper()}
+ % else:
+ 4'b 0001${" " if i == max_regs else ","} // index[${index_str}] ${block.name.upper()}_${r.name.upper()}
+ % endif
+% endfor
+ };
endpackage
+
diff --git a/util/reggen/reg_top.tpl.sv b/util/reggen/reg_top.tpl.sv
index 71fdadd..a23c4e7 100644
--- a/util/reggen/reg_top.tpl.sv
+++ b/util/reggen/reg_top.tpl.sv
@@ -7,6 +7,8 @@
num_wins = len(block.wins)
num_wins_width = ((num_wins+1).bit_length()) - 1
num_dsp = num_wins + 1
+ num_regs = len(block.regs)
+ max_regs_char = len("{}".format(num_regs-1))
%>
module ${block.name}_reg_top (
@@ -43,7 +45,7 @@
logic [DW-1:0] reg_rdata;
logic reg_error;
- logic malformed, addrmiss;
+ logic addrmiss, wr_err;
logic [DW-1:0] reg_rdata_next;
@@ -127,16 +129,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = malformed | addrmiss ;
-
- // Malformed request check only affects to the write access
- always_comb begin : malformed_check
- if (reg_we && (reg_be != '1)) begin
- malformed = 1'b1;
- end else begin
- malformed = 1'b0;
- end
- end
+ assign reg_error = addrmiss | wr_err;
// TODO(eunchan): Revise Register Interface logic after REG INTF finalized
// TODO(eunchan): Make concrete scenario
@@ -236,7 +229,7 @@
always_comb begin
addr_hit = '0;
% for i,r in enumerate(block.regs):
- addr_hit[${i}] = (reg_addr == ${block.name.upper()}_${r.name.upper()}_OFFSET);
+ addr_hit[${"{}".format(i).rjust(max_regs_char)}] = (reg_addr == ${block.name.upper()}_${r.name.upper()}_OFFSET);
% endfor
end
@@ -248,7 +241,14 @@
end
end
- // Write Enable signal
+ // Check sub-word write is permitted
+ always_comb begin
+ wr_err = 1'b0;
+ % for i,r in enumerate(block.regs):
+<% index_str = "{}".format(i).rjust(max_regs_char) %>\
+ if (addr_hit[${index_str}] && reg_we && (${block.name.upper()}_PERMIT[${index_str}] != (${block.name.upper()}_PERMIT[${index_str}] & reg_be))) wr_err = 1'b1 ;
+ % endfor
+ end
% for i, r in enumerate(block.regs):
% if len(r.fields) == 1:
<%
@@ -464,11 +464,11 @@
<%def name="we_gen(sig_name, msb, lsb, swrdaccess, swwraccess, hwext, idx)">\
% if swwraccess != SwWrAccess.NONE:
% if swrdaccess != SwRdAccess.RC:
- assign ${sig_name}_we = addr_hit[${idx}] && reg_we;
+ assign ${sig_name}_we = addr_hit[${idx}] & reg_we & ~wr_err;
assign ${sig_name}_wd = reg_wdata[${str_bits_sv(msb,lsb)}];
% else:
## Generate WE based on read request, read should clear
- assign ${sig_name}_we = addr_hit[${idx}] && reg_re;
+ assign ${sig_name}_we = addr_hit[${idx}] & reg_re;
assign ${sig_name}_wd = '1;
% endif
% endif
