[dv/sram] add UNR coverage
this PR adds the UNR exclusion file,
have discussed these with designer (Michael).
Signed-off-by: Udi Jonnalagadda <udij@google.com>
diff --git a/hw/ip/sram_ctrl/dv/cov/sram_ctrl_unr_excl.el b/hw/ip/sram_ctrl/dv/cov/sram_ctrl_unr_excl.el
new file mode 100644
index 0000000..3c6aaf4
--- /dev/null
+++ b/hw/ip/sram_ctrl/dv/cov/sram_ctrl_unr_excl.el
@@ -0,0 +1,108 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//==================================================
+// This file contains the Excluded objects
+// Generated By User: udij
+// Format Version: 2
+// Date: Mon May 24 14:21:32 2021
+// ExclMode: default
+//==================================================
+CHECKSUM: "418866792 3096942133"
+INSTANCE: tb.dut.u_sram_ctrl.gen_alerts[0].u_prim_alert_sender_parity
+ANNOTATION: "VC_COV_UNR"
+Toggle 0to1 alert_ack_o "logic alert_ack_o"
+ANNOTATION: "VC_COV_UNR"
+Toggle 1to0 alert_ack_o "logic alert_ack_o"
+ANNOTATION: "VC_COV_UNR"
+Toggle 0to1 alert_state_o "logic alert_state_o"
+ANNOTATION: "VC_COV_UNR"
+Toggle 1to0 alert_state_o "logic alert_state_o"
+CHECKSUM: "1684945168 1445297464"
+INSTANCE: tb.dut.u_sram_ctrl
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "908177468" "(init_q && sram_scr_init_i.ack) 1 -1" (1 "01")
+CHECKSUM: "1529365951 19991725"
+INSTANCE: tb.dut.u_tl_adapter_sram
+ANNOTATION: "VC_COV_UNR"
+Condition 6 "1248393269" "(d_valid && rspfifo_rvalid && (reqfifo_rdata.op == OpRead)) 1 -1" (1 "011")
+ANNOTATION: "VC_COV_UNR"
+Condition 8 "4208402038" "(d_valid && d_error) 1 -1" (1 "01")
+CHECKSUM: "2024123546 635059752"
+INSTANCE: tb.dut.u_tl_adapter_sram.u_sramreqfifo
+ANNOTATION: "VC_COV_UNR"
+Condition 1 "644960181" "(gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))) 1 -1" (2 "1")
+CHECKSUM: "3557630994 1702182424"
+INSTANCE: tb.dut.u_sram_ctrl.u_prim_sync_reqack_data.u_prim_sync_reqack
+ANNOTATION: "VC_COV_UNR"
+Block 10 "170878399" ";"
+ANNOTATION: "VC_COV_UNR"
+Block 18 "1804254986" ";"
+CHECKSUM: "418866792 3096942133"
+INSTANCE: tb.dut.u_sram_ctrl.gen_alerts[1].u_prim_alert_sender_parity
+ANNOTATION: "VC_COV_UNR"
+Toggle 1to0 alert_state_o "logic alert_state_o"
+CHECKSUM: "1871869184 1711798198"
+INSTANCE: tb.dut
+ANNOTATION: "VC_COV_UNR"
+Toggle 0to1 csr_tl_o.d_sink [0] "logic csr_tl_o.d_sink[0:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 1to0 csr_tl_o.d_sink [0] "logic csr_tl_o.d_sink[0:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 0to1 csr_tl_o.d_param [0] "logic csr_tl_o.d_param[2:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 1to0 csr_tl_o.d_param [0] "logic csr_tl_o.d_param[2:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 0to1 csr_tl_o.d_param [1] "logic csr_tl_o.d_param[2:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 1to0 csr_tl_o.d_param [1] "logic csr_tl_o.d_param[2:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 0to1 csr_tl_o.d_param [2] "logic csr_tl_o.d_param[2:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 1to0 csr_tl_o.d_param [2] "logic csr_tl_o.d_param[2:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 0to1 sram_tl_o.d_sink [0] "logic sram_tl_o.d_sink[0:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 1to0 sram_tl_o.d_sink [0] "logic sram_tl_o.d_sink[0:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 0to1 sram_tl_o.d_param [0] "logic sram_tl_o.d_param[2:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 1to0 sram_tl_o.d_param [0] "logic sram_tl_o.d_param[2:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 0to1 sram_tl_o.d_param [1] "logic sram_tl_o.d_param[2:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 1to0 sram_tl_o.d_param [1] "logic sram_tl_o.d_param[2:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 0to1 sram_tl_o.d_param [2] "logic sram_tl_o.d_param[2:0]"
+ANNOTATION: "VC_COV_UNR"
+Toggle 1to0 sram_tl_o.d_param [2] "logic sram_tl_o.d_param[2:0]"
+CHECKSUM: "3557630994 2212754372"
+INSTANCE: tb.dut.u_sram_ctrl.u_prim_sync_reqack_data.u_prim_sync_reqack
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "1492303176" "src_fsm_cs" (4) "src_fsm_cs default,-,-"
+ANNOTATION: "VC_COV_UNR"
+Branch 1 "814912860" "dst_fsm_cs" (4) "dst_fsm_cs default,-,-"
+CHECKSUM: "2024123546 2243903072"
+INSTANCE: tb.dut.u_tl_adapter_sram.u_reqfifo
+ANNOTATION: "VC_COV_UNR"
+Branch 3 "2807735941" "(!rst_ni)" (1) "(!rst_ni) 0,1,-,-"
+ANNOTATION: "VC_COV_UNR"
+Branch 4 "1287846560" "(!rst_ni)" (1) "(!rst_ni) 0,1,-,-"
+CHECKSUM: "2024123546 2243903072"
+INSTANCE: tb.dut.u_tl_adapter_sram.u_sramreqfifo
+ANNOTATION: "VC_COV_UNR"
+Branch 0 "1862733684" "gen_normal_fifo.full" (0) "gen_normal_fifo.full 1,-"
+ANNOTATION: "VC_COV_UNR"
+Branch 3 "2807735941" "(!rst_ni)" (1) "(!rst_ni) 0,1,-,-"
+ANNOTATION: "VC_COV_UNR"
+Branch 4 "1287846560" "(!rst_ni)" (1) "(!rst_ni) 0,1,-,-"
+CHECKSUM: "2024123546 4157704780"
+INSTANCE: tb.dut.u_tl_adapter_sram.u_rspfifo
+ANNOTATION: "VC_COV_UNR"
+Branch 4 "2807735941" "(!rst_ni)" (1) "(!rst_ni) 0,1,-,-"
+ANNOTATION: "VC_COV_UNR"
+Branch 5 "1287846560" "(!rst_ni)" (1) "(!rst_ni) 0,1,-,-"
+CHECKSUM: "3754679630 181344662"
+INSTANCE: tb.dut.u_ram1p_sram
+ANNOTATION: "VC_COV_UNR"
+Branch 70 "1538875688" "(!rst_ni)" (1) "(!rst_ni) 0,1"
diff --git a/hw/ip/sram_ctrl/dv/sram_ctrl_base_sim_cfg.hjson b/hw/ip/sram_ctrl/dv/sram_ctrl_base_sim_cfg.hjson
index a6053a7..b80071b 100644
--- a/hw/ip/sram_ctrl/dv/sram_ctrl_base_sim_cfg.hjson
+++ b/hw/ip/sram_ctrl/dv/sram_ctrl_base_sim_cfg.hjson
@@ -40,6 +40,8 @@
// Default iterations for all tests - each test entry can override this.
reseed: 50
+ vcs_cov_excl_files: ["{proj_root}/hw/ip/sram_ctrl/dv/cov/sram_ctrl_cov_unr_excl.el"]
+
// Need to override the default output directory
overrides: [
{
