| commit | 5063497acdf09bb49f5ab4c06e5459cdfd0ec484 | [log] [tgz] |
|---|---|---|
| author | Tom Roberts <tomroberts@lowrisc.org> | Wed Aug 12 08:52:13 2020 +0100 |
| committer | Tom Roberts <53745528+tomroberts-lowrisc@users.noreply.github.com> | Wed Aug 12 11:35:54 2020 +0100 |
| tree | d3bc5db5bb12fde2fd55a1ab159d8d860161f377 | |
| parent | 44d5cabe6cc5c18490eb995a0f02869560b6120b [diff] |
Update lowrisc_ibex to lowRISC/ibex@4c813a0 Update code from upstream repository https://github.com/lowRISC/ibex.git to revision 4c813a0422091d3c0f82df16eb28d2c746c36218 * [ibex/dv] Update OVPsim to use 34-bit address range (Udi) * [rtl] remove lsu_req_in_id signal (Greg Chadwick) * [doc] Fix table rendering in README (Greg Chadwick) * [ibex/ml] Update the ML testlist (Udi) * [ibex] Update CSR description of cpuctrl/secureseed (Udi) * [syn] Use latch-based register file in yosys (Tom Roberts) * [ibex/dv] Update Ibex PMP tests (Udi) * Update google_riscv-dv to google/riscv-dv@61755c0 (Udi) * [ibex/rtl] Fix pmpaddr write enable signal (Udi) * Set `FPGA_XILINX` define whenever Vivado is used (Pirmin Vogel) * [doc] Update FPGA Synthesis Paragraph in Intro (ganoam) * Fix typo in examples/sw/benchmarks/README.md (Yuichi Sugiyama) * Add myself to CREDITS.md (ganoam) * Remove Verible lint workaround (Philipp Wagner) * [dv] Add custom CSRs to yaml description file (Pirmin Vogel) * [dv/ibex] Update CSR listings (Udi) * Update google_riscv-dv to google/riscv-dv@3cf691d (Udi) * Properly vendor in mem_model from OpenTitan (Rupert Swarbrick) * Update lowrisc_ip to lowRISC/opentitan@067272a2 (Rupert Swarbrick) * Track mem_err_shift better in the ICache scoreboard (Rupert Swarbrick) * Minor rejigs to Makefile dvsim wrapper (Rupert Swarbrick) * Remove duplicated files from dv/uvm/core_ibex/common/utils (Rupert Swarbrick) * Define an Ibex-specific top_pkg core (Rupert Swarbrick) * [dvsim] Print a more helpful path to coverage dashboard (Rupert Swarbrick) * [dv] Fix typos (Pirmin Vogel) * [dv/ibex] Enhance riscv_debug_single_step test (Udi) * [rtl] Make sure decoder also checks bits 26 and 25 for slli, srli, srai (Pirmin Vogel) * [rtl] Add security hardened PC (Tom Roberts) * [dv/ibex] Switch to request/response terminology (Udi) * [rtl] Add register-file ECC checking (Tom Roberts) * [rtl] Add alert outputs (Tom Roberts) * [params] Add SecureIbex option to simple system (Tom Roberts) Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
This repository contains hardware, software and utilities written as part of the OpenTitan project. It is structured as monolithic repository, or “monorepo”, where all components live in one repository. It exists to enable collaboration across partners participating in the OpenTitan project.
The project contains comprehensive documentation of all IPs and tools. You can access it online at docs.opentitan.org.
Have a look at CONTRIBUTING for guidelines on how to contribute code to this repository.
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).