[dif/aes] migrate srcs to use autogen'd AES DIF components
This partially addresses #8142.
Signed-off-by: Timothy Trippel <ttrippel@google.com>
diff --git a/hw/top_englishbreakfast/util/sw_sources.patch b/hw/top_englishbreakfast/util/sw_sources.patch
index c59d247..16f08d9 100644
--- a/hw/top_englishbreakfast/util/sw_sources.patch
+++ b/hw/top_englishbreakfast/util/sw_sources.patch
@@ -52,10 +52,10 @@
- mmio_region_write32(reg32, reg_offset, reg_value & mask);
}
diff --git a/sw/device/sca/aes_serial.c b/sw/device/sca/aes_serial.c
-index 901eba868..b19979b89 100644
+index a2087eb4f..d8d347e1e 100644
--- a/sw/device/sca/aes_serial.c
+++ b/sw/device/sca/aes_serial.c
-@@ -203,18 +203,13 @@ int main(void) {
+@@ -201,18 +201,13 @@ int main(void) {
sca_init(kScaTriggerSourceAes, kScaPeripheralAes);
sca_get_uart(&uart1);
@@ -75,7 +75,7 @@
simple_serial_process_packet();
}
diff --git a/sw/device/sca/lib/sca.c b/sw/device/sca/lib/sca.c
-index 3fb4ff13d..e310076c3 100644
+index 093d215b1..dd231b2cc 100644
--- a/sw/device/sca/lib/sca.c
+++ b/sw/device/sca/lib/sca.c
@@ -56,7 +56,6 @@ enum {
@@ -157,7 +157,7 @@
IGNORE_RESULT(dif_clkmgr_gateable_clock_set_enabled(
&clkmgr, CLKMGR_CLK_ENABLES_CLK_USB_PERI_EN_BIT,
diff --git a/sw/device/tests/aes_smoketest.c b/sw/device/tests/aes_smoketest.c
-index 5b995c27f..0ce27b2f1 100644
+index dff8bd9b6..396123ef7 100644
--- a/sw/device/tests/aes_smoketest.c
+++ b/sw/device/tests/aes_smoketest.c
@@ -7,7 +7,6 @@
@@ -168,7 +168,7 @@
#include "sw/device/lib/testing/test_framework/test_main.h"
#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
-@@ -67,9 +66,6 @@ bool test_main(void) {
+@@ -66,9 +65,6 @@ bool test_main(void) {
LOG_INFO("Running AES test");
@@ -176,8 +176,8 @@
- entropy_testutils_boot_mode_init();
-
// Initialise AES.
- dif_aes_params_t params = {
- .base_addr = mmio_region_from_addr(TOP_EARLGREY_AES_BASE_ADDR),
+ CHECK(dif_aes_init(mmio_region_from_addr(TOP_EARLGREY_AES_BASE_ADDR), &aes) ==
+ kDifOk);
diff --git a/sw/device/tests/meson.build b/sw/device/tests/meson.build
index 7abdc2045..829968cb9 100644
--- a/sw/device/tests/meson.build
diff --git a/sw/device/lib/dif/autogen/meson.build b/sw/device/lib/dif/autogen/meson.build
index f56cf78..0963e25 100644
--- a/sw/device/lib/dif/autogen/meson.build
+++ b/sw/device/lib/dif/autogen/meson.build
@@ -2,6 +2,20 @@
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
+# Autogen AES DIF library
+sw_lib_dif_autogen_aes = declare_dependency(
+ link_with: static_library(
+ 'sw_lib_dif_autogen_aes',
+ sources: [
+ hw_ip_aes_reg_h,
+ 'dif_aes_autogen.c',
+ ],
+ dependencies: [
+ sw_lib_mmio,
+ ],
+ )
+)
+
# Autogen UART DIF library
sw_lib_dif_autogen_uart = declare_dependency(
link_with: static_library(
diff --git a/sw/device/lib/dif/dif_aes.c b/sw/device/lib/dif/dif_aes.c
index 2bf34ee..644f4be 100644
--- a/sw/device/lib/dif/dif_aes.c
+++ b/sw/device/lib/dif/dif_aes.c
@@ -46,37 +46,37 @@
} aes_key_field_val_t;
static bool aes_idle(const dif_aes_t *aes) {
- return mmio_region_get_bit32(aes->params.base_addr, AES_STATUS_REG_OFFSET,
+ return mmio_region_get_bit32(aes->base_addr, AES_STATUS_REG_OFFSET,
AES_STATUS_IDLE_BIT);
}
static bool aes_stalled(const dif_aes_t *aes) {
- return mmio_region_get_bit32(aes->params.base_addr, AES_STATUS_REG_OFFSET,
+ return mmio_region_get_bit32(aes->base_addr, AES_STATUS_REG_OFFSET,
AES_STATUS_STALL_BIT);
}
static bool aes_output_lost(const dif_aes_t *aes) {
- return mmio_region_get_bit32(aes->params.base_addr, AES_STATUS_REG_OFFSET,
+ return mmio_region_get_bit32(aes->base_addr, AES_STATUS_REG_OFFSET,
AES_STATUS_OUTPUT_LOST_BIT);
}
static bool aes_output_valid(const dif_aes_t *aes) {
- return mmio_region_get_bit32(aes->params.base_addr, AES_STATUS_REG_OFFSET,
+ return mmio_region_get_bit32(aes->base_addr, AES_STATUS_REG_OFFSET,
AES_STATUS_OUTPUT_VALID_BIT);
}
static bool aes_input_ready(const dif_aes_t *aes) {
- return mmio_region_get_bit32(aes->params.base_addr, AES_STATUS_REG_OFFSET,
+ return mmio_region_get_bit32(aes->base_addr, AES_STATUS_REG_OFFSET,
AES_STATUS_INPUT_READY_BIT);
}
static bool aes_alert_fatal(const dif_aes_t *aes) {
- return mmio_region_get_bit32(aes->params.base_addr, AES_STATUS_REG_OFFSET,
+ return mmio_region_get_bit32(aes->base_addr, AES_STATUS_REG_OFFSET,
AES_STATUS_ALERT_FATAL_FAULT_BIT);
}
static bool aes_alert_recoverable(const dif_aes_t *aes) {
- return mmio_region_get_bit32(aes->params.base_addr, AES_STATUS_REG_OFFSET,
+ return mmio_region_get_bit32(aes->base_addr, AES_STATUS_REG_OFFSET,
AES_STATUS_ALERT_RECOV_CTRL_UPDATE_ERR_BIT);
}
@@ -96,8 +96,7 @@
uint32_t ctrl_reg =
bitfield_bit32_write(0, AES_CTRL_SHADOWED_MANUAL_OPERATION_BIT, true);
- aes_shadowed_write(aes->params.base_addr, AES_CTRL_SHADOWED_REG_OFFSET,
- ctrl_reg);
+ aes_shadowed_write(aes->base_addr, AES_CTRL_SHADOWED_REG_OFFSET, ctrl_reg);
uint32_t trigger_reg =
bitfield_bit32_write(0, AES_TRIGGER_KEY_IV_DATA_IN_CLEAR_BIT, true);
@@ -105,8 +104,7 @@
trigger_reg =
bitfield_bit32_write(trigger_reg, AES_TRIGGER_DATA_OUT_CLEAR_BIT, true);
- mmio_region_write32(aes->params.base_addr, AES_TRIGGER_REG_OFFSET,
- trigger_reg);
+ mmio_region_write32(aes->base_addr, AES_TRIGGER_REG_OFFSET, trigger_reg);
// Make sure AES is cleared before proceeding (may take multiple cycles).
while (!aes_idle(aes)) {
@@ -132,14 +130,14 @@
* @param aes AES state data.
* @param transaction Configuration data, common across all Cipher modes.
* @param cipher_mode_val Cipher Mode register write value.
- * @return `dif_aes_start_result_t`.
+ * @return `dif_result_t`.
*/
-static dif_aes_result_t configure(const dif_aes_t *aes,
- const dif_aes_transaction_t *transaction,
- aes_mode_field_val_t cipher_mode_val) {
+static dif_result_t configure(const dif_aes_t *aes,
+ const dif_aes_transaction_t *transaction,
+ aes_mode_field_val_t cipher_mode_val) {
aes_key_field_val_t key_len_val = key_to_field(transaction->key_len);
if (key_len_val == kAesKeyFieldValInvalid) {
- return kDifAesError;
+ return kDifError;
}
uint32_t reg =
@@ -170,9 +168,9 @@
false);
}
- aes_shadowed_write(aes->params.base_addr, AES_CTRL_SHADOWED_REG_OFFSET, reg);
+ aes_shadowed_write(aes->base_addr, AES_CTRL_SHADOWED_REG_OFFSET, reg);
- return kDifAesOk;
+ return kDifOk;
}
/**
@@ -188,23 +186,23 @@
for (int i = 0; i < regs_num; ++i) {
ptrdiff_t offset = reg0_offset + (i * sizeof(uint32_t));
- mmio_region_write32(aes->params.base_addr, offset, data[i]);
+ mmio_region_write32(aes->base_addr, offset, data[i]);
}
}
-dif_aes_result_t dif_aes_init(dif_aes_params_t params, dif_aes_t *aes) {
+dif_result_t dif_aes_init(mmio_region_t base_addr, dif_aes_t *aes) {
if (aes == NULL) {
- return kDifAesBadArg;
+ return kDifBadArg;
}
- aes->params = params;
+ aes->base_addr = base_addr;
- return kDifAesOk;
+ return kDifOk;
}
-dif_aes_result_t dif_aes_reset(const dif_aes_t *aes) {
+dif_result_t dif_aes_reset(const dif_aes_t *aes) {
if (aes == NULL) {
- return kDifAesBadArg;
+ return kDifBadArg;
}
aes_clear_internal_state(aes);
@@ -219,24 +217,24 @@
reg =
bitfield_field32_write(reg, AES_CTRL_SHADOWED_KEY_LEN_FIELD, 0xffffffff);
- aes_shadowed_write(aes->params.base_addr, AES_CTRL_SHADOWED_REG_OFFSET, reg);
+ aes_shadowed_write(aes->base_addr, AES_CTRL_SHADOWED_REG_OFFSET, reg);
- return kDifAesOk;
+ return kDifOk;
}
-dif_aes_result_t dif_aes_start_ecb(const dif_aes_t *aes,
- const dif_aes_transaction_t *transaction,
- dif_aes_key_share_t key) {
+dif_result_t dif_aes_start_ecb(const dif_aes_t *aes,
+ const dif_aes_transaction_t *transaction,
+ dif_aes_key_share_t key) {
if (aes == NULL || transaction == NULL) {
- return kDifAesBadArg;
+ return kDifBadArg;
}
if (!aes_idle(aes)) {
- return kDifAesBusy;
+ return kDifIpBusy;
}
- dif_aes_result_t result = configure(aes, transaction, kAesModeFieldValEcb);
- if (result != kDifAesOk) {
+ dif_result_t result = configure(aes, transaction, kAesModeFieldValEcb);
+ if (result != kDifOk) {
return result;
}
@@ -246,22 +244,22 @@
aes_set_multireg(aes, &key.share1[0], AES_KEY_SHARE1_MULTIREG_COUNT,
AES_KEY_SHARE1_0_REG_OFFSET);
- return kDifAesOk;
+ return kDifOk;
}
-dif_aes_result_t dif_aes_start_cbc(const dif_aes_t *aes,
- const dif_aes_transaction_t *transaction,
- dif_aes_key_share_t key, dif_aes_iv_t iv) {
+dif_result_t dif_aes_start_cbc(const dif_aes_t *aes,
+ const dif_aes_transaction_t *transaction,
+ dif_aes_key_share_t key, dif_aes_iv_t iv) {
if (aes == NULL || transaction == NULL) {
- return kDifAesBadArg;
+ return kDifBadArg;
}
if (!aes_idle(aes)) {
- return kDifAesBusy;
+ return kDifIpBusy;
}
- dif_aes_result_t result = configure(aes, transaction, kAesModeFieldValCbc);
- if (result != kDifAesOk) {
+ dif_result_t result = configure(aes, transaction, kAesModeFieldValCbc);
+ if (result != kDifOk) {
return result;
}
@@ -273,22 +271,22 @@
aes_set_multireg(aes, &iv.iv[0], AES_IV_MULTIREG_COUNT, AES_IV_0_REG_OFFSET);
- return kDifAesOk;
+ return kDifOk;
}
-dif_aes_result_t dif_aes_start_ctr(const dif_aes_t *aes,
- const dif_aes_transaction_t *transaction,
- dif_aes_key_share_t key, dif_aes_iv_t iv) {
+dif_result_t dif_aes_start_ctr(const dif_aes_t *aes,
+ const dif_aes_transaction_t *transaction,
+ dif_aes_key_share_t key, dif_aes_iv_t iv) {
if (aes == NULL || transaction == NULL) {
- return kDifAesBadArg;
+ return kDifBadArg;
}
if (!aes_idle(aes)) {
- return kDifAesBusy;
+ return kDifIpBusy;
}
- dif_aes_result_t result = configure(aes, transaction, kAesModeFieldValCtr);
- if (result != kDifAesOk) {
+ dif_result_t result = configure(aes, transaction, kAesModeFieldValCtr);
+ if (result != kDifOk) {
return result;
}
@@ -300,62 +298,60 @@
aes_set_multireg(aes, &iv.iv[0], AES_IV_MULTIREG_COUNT, AES_IV_0_REG_OFFSET);
- return kDifAesOk;
+ return kDifOk;
}
-dif_aes_result_t dif_aes_end(const dif_aes_t *aes) {
+dif_result_t dif_aes_end(const dif_aes_t *aes) {
if (aes == NULL) {
- return kDifAesBadArg;
+ return kDifBadArg;
}
if (!aes_idle(aes)) {
- return kDifAesBusy;
+ return kDifIpBusy;
}
aes_clear_internal_state(aes);
- return kDifAesOk;
+ return kDifOk;
}
-dif_aes_result_t dif_aes_load_data(const dif_aes_t *aes,
- const dif_aes_data_t data) {
+dif_result_t dif_aes_load_data(const dif_aes_t *aes,
+ const dif_aes_data_t data) {
if (aes == NULL) {
- return kDifAesBadArg;
+ return kDifBadArg;
}
if (!aes_input_ready(aes)) {
- return kDifAesBusy;
+ return kDifIpBusy;
}
aes_set_multireg(aes, &data.data[0], AES_DATA_IN_MULTIREG_COUNT,
AES_DATA_IN_0_REG_OFFSET);
- return kDifAesOk;
+ return kDifOk;
}
-dif_aes_result_t dif_aes_read_output(const dif_aes_t *aes,
- dif_aes_data_t *data) {
+dif_result_t dif_aes_read_output(const dif_aes_t *aes, dif_aes_data_t *data) {
if (aes == NULL || data == NULL) {
- return kDifAesBadArg;
+ return kDifBadArg;
}
if (!aes_output_valid(aes)) {
- return kDifAesOutputInvalid;
+ return kDifError;
}
for (int i = 0; i < AES_DATA_OUT_MULTIREG_COUNT; ++i) {
ptrdiff_t offset = AES_DATA_OUT_0_REG_OFFSET + (i * sizeof(uint32_t));
- data->data[i] = mmio_region_read32(aes->params.base_addr, offset);
+ data->data[i] = mmio_region_read32(aes->base_addr, offset);
}
- return kDifAesOk;
+ return kDifOk;
}
-dif_aes_result_t dif_aes_trigger(const dif_aes_t *aes,
- dif_aes_trigger_t trigger) {
+dif_result_t dif_aes_trigger(const dif_aes_t *aes, dif_aes_trigger_t trigger) {
if (aes == NULL) {
- return kDifAesBadArg;
+ return kDifBadArg;
}
uint32_t reg;
@@ -373,18 +369,18 @@
reg = bitfield_bit32_write(0, AES_TRIGGER_PRNG_RESEED_BIT, true);
break;
default:
- return kDifAesError;
+ return kDifError;
}
- mmio_region_write32(aes->params.base_addr, AES_TRIGGER_REG_OFFSET, reg);
+ mmio_region_write32(aes->base_addr, AES_TRIGGER_REG_OFFSET, reg);
- return kDifAesOk;
+ return kDifOk;
}
-dif_aes_result_t dif_aes_get_status(const dif_aes_t *aes, dif_aes_status_t flag,
- bool *set) {
+dif_result_t dif_aes_get_status(const dif_aes_t *aes, dif_aes_status_t flag,
+ bool *set) {
if (aes == NULL || set == NULL) {
- return kDifAesBadArg;
+ return kDifBadArg;
}
switch (flag) {
@@ -410,17 +406,16 @@
*set = aes_alert_recoverable(aes);
break;
default:
- return kDifAesError;
+ return kDifError;
}
- return kDifAesOk;
+ return kDifOk;
}
OT_WARN_UNUSED_RESULT
-dif_aes_result_t dif_aes_alert_force(const dif_aes_t *aes,
- dif_aes_alert_t alert) {
+dif_result_t dif_aes_alert_force(const dif_aes_t *aes, dif_aes_alert_t alert) {
if (aes == NULL) {
- return kDifAesBadArg;
+ return kDifBadArg;
}
bitfield_bit32_index_t index;
@@ -432,11 +427,11 @@
index = AES_ALERT_TEST_RECOV_CTRL_UPDATE_ERR_BIT;
break;
default:
- return kDifAesError;
+ return kDifError;
}
uint32_t reg = bitfield_bit32_write(0, index, true);
- mmio_region_write32(aes->params.base_addr, AES_ALERT_TEST_REG_OFFSET, reg);
+ mmio_region_write32(aes->base_addr, AES_ALERT_TEST_REG_OFFSET, reg);
- return kDifAesOk;
+ return kDifOk;
}
diff --git a/sw/device/lib/dif/dif_aes.h b/sw/device/lib/dif/dif_aes.h
index ea07922..b43e429 100644
--- a/sw/device/lib/dif/dif_aes.h
+++ b/sw/device/lib/dif/dif_aes.h
@@ -10,6 +10,9 @@
#include "sw/device/lib/base/macros.h"
#include "sw/device/lib/base/mmio.h"
+#include "sw/device/lib/dif/dif_base.h"
+
+#include "sw/device/lib/dif/autogen/dif_aes_autogen.h"
#ifdef __cplusplus
extern "C" {
@@ -170,68 +173,16 @@
} dif_aes_alert_t;
/**
- * Hardware instantiation parameters for AES.
- *
- * This struct describes information about the underlying hardware that is
- * not determined until the hardware design is used as part of a top-level
- * design.
- */
-typedef struct dif_aes_params {
- /**
- * The base address for the AES hardware registers.
- */
- mmio_region_t base_addr;
-} dif_aes_params_t;
-
-/**
- * A handle to AES.
- *
- * This type should be treated as opaque by users.
- */
-typedef struct dif_aes {
- dif_aes_params_t params;
-} dif_aes_t;
-
-/**
- * The result of a AES operation.
- */
-typedef enum dif_aes_result {
- /**
- * Indicates that the operation succeeded.
- */
- kDifAesOk = 0,
- /**
- * Indicates some unspecified failure.
- */
- kDifAesError = 1,
- /**
- * Indicates that some parameter passed into a function failed a
- * precondition.
- *
- * When this value is returned, no hardware operations occurred.
- */
- kDifAesBadArg = 2,
- /**
- * Device is busy, and cannot perform the requested operation.
- */
- kDifAesBusy,
- /**
- * The AES unit has no valid output.
- */
- kDifAesOutputInvalid,
-} dif_aes_result_t;
-
-/**
* Creates a new handle for AES.
*
* This function does not actuate the hardware.
*
- * @param params Hardware instantiation parameters.
+ * @param base_addr Hardware instantiation base address.
* @param[out] aes Out param for the initialised handle.
* @return The result of the operation.
*/
OT_WARN_UNUSED_RESULT
-dif_aes_result_t dif_aes_init(dif_aes_params_t params, dif_aes_t *aes);
+dif_result_t dif_aes_init(mmio_region_t base_addr, dif_aes_t *aes);
/**
* Resets an instance of AES.
@@ -242,7 +193,7 @@
* @return The result of the operation.
*/
OT_WARN_UNUSED_RESULT
-dif_aes_result_t dif_aes_reset(const dif_aes_t *aes);
+dif_result_t dif_aes_reset(const dif_aes_t *aes);
/**
* Begins an AES transaction in ECB mode.
@@ -264,9 +215,9 @@
* @return The result of the operation.
*/
OT_WARN_UNUSED_RESULT
-dif_aes_result_t dif_aes_start_ecb(const dif_aes_t *aes,
- const dif_aes_transaction_t *transaction,
- dif_aes_key_share_t key);
+dif_result_t dif_aes_start_ecb(const dif_aes_t *aes,
+ const dif_aes_transaction_t *transaction,
+ dif_aes_key_share_t key);
/**
* Begins an AES transaction in CBC mode.
@@ -291,9 +242,9 @@
* @return The result of the operation.
*/
OT_WARN_UNUSED_RESULT
-dif_aes_result_t dif_aes_start_cbc(const dif_aes_t *aes,
- const dif_aes_transaction_t *transaction,
- dif_aes_key_share_t key, dif_aes_iv_t iv);
+dif_result_t dif_aes_start_cbc(const dif_aes_t *aes,
+ const dif_aes_transaction_t *transaction,
+ dif_aes_key_share_t key, dif_aes_iv_t iv);
/**
* Begins an AES transaction in CTR mode.
@@ -316,9 +267,9 @@
* @return The result of the operation.
*/
OT_WARN_UNUSED_RESULT
-dif_aes_result_t dif_aes_start_ctr(const dif_aes_t *aes,
- const dif_aes_transaction_t *transaction,
- dif_aes_key_share_t key, dif_aes_iv_t iv);
+dif_result_t dif_aes_start_ctr(const dif_aes_t *aes,
+ const dif_aes_transaction_t *transaction,
+ dif_aes_key_share_t key, dif_aes_iv_t iv);
/**
* Ends an AES transaction.
@@ -333,7 +284,7 @@
* @return The result of the operation.
*/
OT_WARN_UNUSED_RESULT
-dif_aes_result_t dif_aes_end(const dif_aes_t *aes);
+dif_result_t dif_aes_end(const dif_aes_t *aes);
/**
* Loads AES Input Data.
@@ -349,8 +300,7 @@
* @return The result of the operation.
*/
OT_WARN_UNUSED_RESULT
-dif_aes_result_t dif_aes_load_data(const dif_aes_t *aes,
- const dif_aes_data_t data);
+dif_result_t dif_aes_load_data(const dif_aes_t *aes, const dif_aes_data_t data);
/**
* Reads AES Output Data.
@@ -364,8 +314,7 @@
* @return The result of the operation.
*/
OT_WARN_UNUSED_RESULT
-dif_aes_result_t dif_aes_read_output(const dif_aes_t *aes,
- dif_aes_data_t *data);
+dif_result_t dif_aes_read_output(const dif_aes_t *aes, dif_aes_data_t *data);
/**
* AES Trigger flags.
@@ -400,8 +349,7 @@
* @return The result of the operation.
*/
OT_WARN_UNUSED_RESULT
-dif_aes_result_t dif_aes_trigger(const dif_aes_t *aes,
- dif_aes_trigger_t trigger);
+dif_result_t dif_aes_trigger(const dif_aes_t *aes, dif_aes_trigger_t trigger);
/**
* AES Status flags.
@@ -453,8 +401,8 @@
* @return The result of the operation.
*/
OT_WARN_UNUSED_RESULT
-dif_aes_result_t dif_aes_get_status(const dif_aes_t *aes, dif_aes_status_t flag,
- bool *set);
+dif_result_t dif_aes_get_status(const dif_aes_t *aes, dif_aes_status_t flag,
+ bool *set);
/**
* Forces a particular alert, causing it to be serviced as if hardware had
@@ -465,8 +413,7 @@
* @return The result of the operation.
*/
OT_WARN_UNUSED_RESULT
-dif_aes_result_t dif_aes_alert_force(const dif_aes_t *aes,
- dif_aes_alert_t alert);
+dif_result_t dif_aes_alert_force(const dif_aes_t *aes, dif_aes_alert_t alert);
#ifdef __cplusplus
} // extern "C"
diff --git a/sw/device/lib/dif/meson.build b/sw/device/lib/dif/meson.build
index e09fdb7..d8a306b 100644
--- a/sw/device/lib/dif/meson.build
+++ b/sw/device/lib/dif/meson.build
@@ -647,16 +647,21 @@
hw_ip_aes_reg_h,
'dif_aes.c',
],
- dependencies: [sw_lib_mmio],
+ dependencies: [
+ sw_lib_mmio,
+ sw_lib_dif_autogen_aes,
+ ],
)
)
test('dif_aes_unittest', executable(
'dif_aes_unittest',
sources: [
- hw_ip_aes_reg_h,
- meson.source_root() / 'sw/device/lib/dif/dif_aes.c',
'dif_aes_unittest.cc',
+ 'autogen/dif_aes_autogen_unittest.cc',
+ meson.source_root() / 'sw/device/lib/dif/dif_aes.c',
+ meson.source_root() / 'sw/device/lib/dif/autogen/dif_aes_autogen.c',
+ hw_ip_aes_reg_h,
],
dependencies: [
sw_vendor_gtest,
diff --git a/sw/device/sca/aes_serial.c b/sw/device/sca/aes_serial.c
index 901eba8..a2087eb 100644
--- a/sw/device/sca/aes_serial.c
+++ b/sw/device/sca/aes_serial.c
@@ -62,14 +62,14 @@
dif_aes_key_share_t key_shares;
memcpy(key_shares.share0, key, sizeof(key_shares.share0));
memset(key_shares.share1, 0, sizeof(key_shares.share1));
- SS_CHECK(dif_aes_start_ecb(&aes, &transaction, key_shares) == kDifAesOk);
+ SS_CHECK(dif_aes_start_ecb(&aes, &transaction, key_shares) == kDifOk);
}
/**
* Callback wrapper for AES manual trigger function.
*/
static void aes_manual_trigger(void) {
- SS_CHECK(dif_aes_trigger(&aes, kDifAesTriggerStart) == kDifAesOk);
+ SS_CHECK(dif_aes_trigger(&aes, kDifAesTriggerStart) == kDifOk);
}
/**
@@ -87,12 +87,12 @@
bool ready = false;
do {
SS_CHECK(dif_aes_get_status(&aes, kDifAesStatusInputReady, &ready) ==
- kDifAesOk);
+ kDifOk);
} while (!ready);
dif_aes_data_t data;
SS_CHECK(plaintext_len <= sizeof(data.data));
memcpy(data.data, plaintext, plaintext_len);
- SS_CHECK(dif_aes_load_data(&aes, data) == kDifAesOk);
+ SS_CHECK(dif_aes_load_data(&aes, data) == kDifOk);
// Start AES operation (this triggers the capture) and go to sleep.
// Using the SecAesStartTriggerDelay hardware parameter, the AES unit is
@@ -122,11 +122,11 @@
bool ready = false;
do {
SS_CHECK(dif_aes_get_status(&aes, kDifAesStatusOutputValid, &ready) ==
- kDifAesOk);
+ kDifOk);
} while (!ready);
dif_aes_data_t ciphertext;
- SS_CHECK(dif_aes_read_output(&aes, &ciphertext) == kDifAesOk);
+ SS_CHECK(dif_aes_read_output(&aes, &ciphertext) == kDifOk);
simple_serial_send_packet('r', (uint8_t *)ciphertext.data,
sizeof(ciphertext.data));
}
@@ -171,11 +171,11 @@
bool ready = false;
do {
SS_CHECK(dif_aes_get_status(&aes, kDifAesStatusOutputValid, &ready) ==
- kDifAesOk);
+ kDifOk);
} while (!ready);
dif_aes_data_t ciphertext;
- SS_CHECK(dif_aes_read_output(&aes, &ciphertext) == kDifAesOk);
+ SS_CHECK(dif_aes_read_output(&aes, &ciphertext) == kDifOk);
simple_serial_send_packet('r', (uint8_t *)ciphertext.data,
sizeof(ciphertext.data));
}
@@ -184,11 +184,9 @@
* Initializes the AES peripheral.
*/
static void init_aes(void) {
- dif_aes_params_t params = {
- .base_addr = mmio_region_from_addr(TOP_EARLGREY_AES_BASE_ADDR),
- };
- SS_CHECK(dif_aes_init(params, &aes) == kDifAesOk);
- SS_CHECK(dif_aes_reset(&aes) == kDifAesOk);
+ SS_CHECK(dif_aes_init(mmio_region_from_addr(TOP_EARLGREY_AES_BASE_ADDR),
+ &aes) == kDifOk);
+ SS_CHECK(dif_aes_reset(&aes) == kDifOk);
}
/**
diff --git a/sw/device/tests/aes_smoketest.c b/sw/device/tests/aes_smoketest.c
index 5b995c2..dff8bd9 100644
--- a/sw/device/tests/aes_smoketest.c
+++ b/sw/device/tests/aes_smoketest.c
@@ -49,15 +49,14 @@
static bool aes_input_ready(const dif_aes_t *aes) {
bool status;
- CHECK(dif_aes_get_status(aes, kDifAesStatusInputReady, &status) == kDifAesOk);
+ CHECK(dif_aes_get_status(aes, kDifAesStatusInputReady, &status) == kDifOk);
return status;
}
static bool aes_output_valid(const dif_aes_t *aes) {
bool status;
- CHECK(dif_aes_get_status(aes, kDifAesStatusOutputValid, &status) ==
- kDifAesOk);
+ CHECK(dif_aes_get_status(aes, kDifAesStatusOutputValid, &status) == kDifOk);
return status;
}
@@ -71,11 +70,9 @@
entropy_testutils_boot_mode_init();
// Initialise AES.
- dif_aes_params_t params = {
- .base_addr = mmio_region_from_addr(TOP_EARLGREY_AES_BASE_ADDR),
- };
- CHECK(dif_aes_init(params, &aes) == kDifAesOk);
- CHECK(dif_aes_reset(&aes) == kDifAesOk);
+ CHECK(dif_aes_init(mmio_region_from_addr(TOP_EARLGREY_AES_BASE_ADDR), &aes) ==
+ kDifOk);
+ CHECK(dif_aes_reset(&aes) == kDifOk);
// Mask the key. Note that this should not be done manually. Software is
// expected to get the key in two shares right from the beginning.
@@ -95,7 +92,7 @@
.mode = kDifAesModeEncrypt,
.operation = kDifAesOperationAuto,
};
- CHECK(dif_aes_start_ecb(&aes, &transaction, key) == kDifAesOk);
+ CHECK(dif_aes_start_ecb(&aes, &transaction, key) == kDifOk);
// "Convert" plain data byte arrays to `dif_aes_data_t`.
dif_aes_data_t in_data_plain;
@@ -104,16 +101,16 @@
// Load the plain text to trigger the encryption operation.
while (!aes_input_ready(&aes)) {
}
- CHECK(dif_aes_load_data(&aes, in_data_plain) == kDifAesOk);
+ CHECK(dif_aes_load_data(&aes, in_data_plain) == kDifOk);
// Read out the produced cipher text.
dif_aes_data_t out_data_cipher;
while (!aes_output_valid(&aes)) {
}
- CHECK(dif_aes_read_output(&aes, &out_data_cipher) == kDifAesOk);
+ CHECK(dif_aes_read_output(&aes, &out_data_cipher) == kDifOk);
// Finish the ECB encryption transaction.
- CHECK(dif_aes_end(&aes) == kDifAesOk);
+ CHECK(dif_aes_end(&aes) == kDifOk);
// Check the produced cipher text against the reference.
uint32_t cipher_text_gold_words[TEXT_LENGTH_IN_WORDS];
@@ -126,22 +123,22 @@
// Setup ECB decryption transaction.
transaction.mode = kDifAesModeDecrypt;
- CHECK(dif_aes_start_ecb(&aes, &transaction, key) == kDifAesOk);
+ CHECK(dif_aes_start_ecb(&aes, &transaction, key) == kDifOk);
// Load the previously produced cipher text to start the decryption operation.
while (!aes_input_ready(&aes)) {
}
- CHECK(dif_aes_load_data(&aes, out_data_cipher) == kDifAesOk);
+ CHECK(dif_aes_load_data(&aes, out_data_cipher) == kDifOk);
// Read out the produced plain text.
dif_aes_data_t out_data_plain;
while (!aes_output_valid(&aes)) {
}
- CHECK(dif_aes_read_output(&aes, &out_data_plain) == kDifAesOk);
+ CHECK(dif_aes_read_output(&aes, &out_data_plain) == kDifOk);
// Finish the ECB encryption transaction.
- CHECK(dif_aes_end(&aes) == kDifAesOk);
+ CHECK(dif_aes_end(&aes) == kDifOk);
// Check the produced plain text against the reference.
uint32_t plain_text_gold_words[TEXT_LENGTH_IN_WORDS];
