| commit | 4fc169f1635b39b8131ffa668a35422b968e9964 | [log] [tgz] |
|---|---|---|
| author | Eunchan Kim <eunchan@google.com> | Wed Oct 23 22:53:05 2019 -0700 |
| committer | Eunchan Kim <eunchan@google.com> | Thu Oct 24 15:50:25 2019 -0700 |
| tree | 9224ee1009998568e4931ba4d61dd946a4ba7eb6 | |
| parent | e34ccdc62e89fef3fbb7382bba64d4bb4817150c [diff] |
[rv_plic] Latch to CC for pending interrupts
This is related to #577. @GregAC reported this bug while reviewing the
RV_PLIC specification.
Error:
RISC-V PLIC assumes the Claim/Complete register can be polled by the
software even the interrupt pending bit (mip) isn't set. The RV_PLIC
design only set the CC0 register when the priority is greater than
the threshold value.
From the RISCV PLIC Spec:
> It is always legal for a hart to perform a claim even if the EIP is
> not set. In particular, a hart could set the threshold value to
> maximum to disable interrupt notifications and instead poll for active
> interrupts using periodic claim requests, though a simpler approach to
> implement polling would be to clear the external interrupt enable in
> the corresponding xie register for privilege mode x.
https://github.com/riscv/riscv-isa-manual/blob/master/src/plic.tex#L329-L334
For instance, if the `threshold` value is set to 7h while the MAX_PRIO
is set to 7 and ID 1 interrupt is pending, the `irq_o` of the RV_PLIC IP
will never be asserted. In this case, `CC0` register of the previous
version showed value `0` always. What spec expects is to be visible of
the most highest priority pending interrupt, which is, in this case, ID
1.
Solution:
Revise the logic not to consider threshold to calculate `irq_id` in
the target module. But `irq` should consider the threshold value
comparing with max priority calculated.
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