commit | 9f5b638736ea1c3f20b72d31b9969d6e6ebc230b | [log] [tgz] |
---|---|---|
author | Greg Chadwick <gac@lowrisc.org> | Mon May 10 17:53:46 2021 +0100 |
committer | Greg Chadwick <gac@lowrisc.org> | Tue May 11 09:05:39 2021 +0100 |
tree | 7f8af1f11648f0c0dd728d8350759f4b91340685 | |
parent | 1759b4b7de6624b3cdaf941c7c841f13b2135085 [diff] |
[otbn] Fix error when using the last x1 value as a base address This refactors the use of `rd_base_rd_commit_o` vs `rd_base_rd_en_a_o` and `rd_base_en_b_o`. Previously for any instruction that was stalled, `rd_base_en_a_o` and `rd_base_en_b_o` would remain asserted for the whole instruction, with `rd_base_rd_commit_o` used to indicate the cycle the read actually occurred (in particular when to pop the call stack if `x1` was being a read). This caused an issue with `call_stack_err_o` as it doesn't factor in `rd_base_rd_commit_o` to avoid a combinational loop. `call_stack_err_o` could be asserted the second cycle of a load or store where `rd_base_commit_o` isn't asserted but `rd_base_en_a_o` or `rd_base_en_b_o` could be. Now `rd_base_en_a_o` and `rd_base_en_b_o` will only be asserted the cycle the read actually occurrs, assuming no errors. `rd_base_rd_commit_o` prevents the read from occurring if there is an error. Signed-off-by: Greg Chadwick <gac@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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