[reggen] Delete duplicate Register/MultiRegister types in data.py

We've recently moved to representing registers, fields etc. in
classes, rather than dicts. This duplicated some work done in
gen_rtl.py and data.py and this commit removes the duplicated Register
and MultiRegister types.

There's a certain amount of tidying up in reg_pkg.sv.tpl, which I
think makes the implementation a bit easier to read (as much as is
possible for template code like this).

Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>

util/reggen/reg_top.sv.tpl

diff --git a/util/reggen/reg_top.sv.tpl b/util/reggen/reg_top.sv.tpl
index 75bafaf..2fbdf9b 100644
--- a/util/reggen/reg_top.sv.tpl
+++ b/util/reggen/reg_top.sv.tpl
@@ -5,6 +5,8 @@
 // Register Top module auto-generated by `reggen`
 <%
   from reggen.data import get_basename
+  from reggen.register import Register
+  from reggen.multi_register import MultiRegister
 
   num_wins = len(block.wins)
   num_wins_width = ((num_wins+1).bit_length()) - 1
@@ -146,10 +148,10 @@
   //        or <reg>_{wd|we|qs} if field == 1 or 0
   % for r in regs_flat:
     % if len(r.fields) == 1:
-${sig_gen(r.fields[0], r.name, r.hwext, r.shadowed)}\
+${sig_gen(r.fields[0], r.name.lower(), r.hwext, r.shadowed)}\
     % else:
       % for f in r.fields:
-${sig_gen(f, r.name + "_" + f.name.lower(), r.hwext, r.shadowed)}\
+${sig_gen(f, r.name.lower() + "_" + f.name.lower(), r.hwext, r.shadowed)}\
       % endfor
     % endif
   % endfor
@@ -157,37 +159,36 @@
   // Register instances
   % for r in block.regs:
   ######################## multiregister ###########################
-    % if r.is_multi_reg():
+    % if isinstance(r, MultiRegister):
 <%
-      mreg_flat = r.get_regs_flat()
       k = 0
 %>
-      % for sr in mreg_flat:
-  // Subregister ${k} of Multireg ${r.name}
-  // R[${sr.name}]: V(${str(sr.hwext)})
+      % for sr in r.regs:
+  // Subregister ${k} of Multireg ${r.reg.name.lower()}
+  // R[${sr.name.lower()}]: V(${str(sr.hwext)})
         % if len(sr.fields) == 1:
 <%
           f = sr.fields[0]
-          finst_name = sr.name
-          fsig_name = r.name + "[%d]" % k
+          finst_name = sr.name.lower()
+          fsig_name = r.reg.name.lower() + "[%d]" % k
           k = k + 1
 %>
 ${finst_gen(f, finst_name, fsig_name, sr.hwext, sr.regwen, sr.shadowed)}
         % else:
           % for f in sr.fields:
 <%
-            finst_name = sr.name + "_" + f.name.lower()
-            if r.ishomog:
-              fsig_name = r.name + "[%d]" % k
+            finst_name = sr.name.lower() + "_" + f.name.lower()
+            if r.is_homogeneous():
+              fsig_name = r.reg.name.lower() + "[%d]" % k
               k = k + 1
             else:
-              fsig_name = r.name + "[%d]" % k + "." + get_basename(f.name.lower())
+              fsig_name = r.reg.name.lower() + "[%d]" % k + "." + get_basename(f.name.lower())
 %>
   // F[${f.name.lower()}]: ${f.bits.msb}:${f.bits.lsb}
 ${finst_gen(f, finst_name, fsig_name, sr.hwext, sr.regwen, sr.shadowed)}
           % endfor
 <%
-          if not r.ishomog:
+          if not r.is_homogeneous():
             k += 1
 %>
         % endif
@@ -195,20 +196,20 @@
       % endfor
 ######################## register with single field ###########################
     % elif len(r.fields) == 1:
-  // R[${r.name}]: V(${str(r.hwext)})
+  // R[${r.name.lower()}]: V(${str(r.hwext)})
 <%
         f = r.fields[0]
-        finst_name = r.name
-        fsig_name = r.name
+        finst_name = r.name.lower()
+        fsig_name = r.name.lower()
 %>
 ${finst_gen(f, finst_name, fsig_name, r.hwext, r.regwen, r.shadowed)}
 ######################## register with multiple fields ###########################
     % else:
-  // R[${r.name}]: V(${str(r.hwext)})
+  // R[${r.name.lower()}]: V(${str(r.hwext)})
       % for f in r.fields:
 <%
-        finst_name = r.name + "_" + f.name.lower()
-        fsig_name = r.name + "." + f.name.lower()
+        finst_name = r.name.lower() + "_" + f.name.lower()
+        fsig_name = r.name.lower() + "." + f.name.lower()
 %>
   //   F[${f.name.lower()}]: ${f.bits.msb}:${f.bits.lsb}
 ${finst_gen(f, finst_name, fsig_name, r.hwext, r.regwen, r.shadowed)}
@@ -239,10 +240,10 @@
   end
   % for i, r in enumerate(regs_flat):
     % if len(r.fields) == 1:
-${we_gen(r.fields[0], r.name, r.hwext, r.shadowed, i)}\
+${we_gen(r.fields[0], r.name.lower(), r.hwext, r.shadowed, i)}\
     % else:
       % for f in r.fields:
-${we_gen(f, r.name + "_" + f.name.lower(), r.hwext, r.shadowed, i)}\
+${we_gen(f, r.name.lower() + "_" + f.name.lower(), r.hwext, r.shadowed, i)}\
       % endfor
     % endif
   % endfor
@@ -254,13 +255,13 @@
       % for i, r in enumerate(regs_flat):
         % if len(r.fields) == 1:
       addr_hit[${i}]: begin
-${rdata_gen(r.fields[0], r.name)}\
+${rdata_gen(r.fields[0], r.name.lower())}\
       end
 
         % else:
       addr_hit[${i}]: begin
           % for f in r.fields:
-${rdata_gen(f, r.name + "_" + f.name.lower())}\
+${rdata_gen(f, r.name.lower() + "_" + f.name.lower())}\
           % endfor
       end
 
@@ -322,7 +323,7 @@
     % if field.swaccess.allows_write():
       % if regwen:
     // qualified with register enable
-    .we     (${finst_name}_we & ${regwen}_qs),
+    .we     (${finst_name}_we & ${regwen.lower()}_qs),
       % else:
     .we     (${finst_name}_we),
       % endif
@@ -384,7 +385,7 @@
       % if field.swaccess.allows_write(): ## non-RO types
         % if regwen:
     // from register interface (qualified with register enable)
-    .we     (${finst_name}_we & ${regwen}_qs),
+    .we     (${finst_name}_we & ${regwen.lower()}_qs),
         % else:
     // from register interface
     .we     (${finst_name}_we),