[reggen] Delete duplicate Register/MultiRegister types in data.py We've recently moved to representing registers, fields etc. in classes, rather than dicts. This duplicated some work done in gen_rtl.py and data.py and this commit removes the duplicated Register and MultiRegister types. There's a certain amount of tidying up in reg_pkg.sv.tpl, which I think makes the implementation a bit easier to read (as much as is possible for template code like this). Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
diff --git a/util/reggen/fpv_csr.sv.tpl b/util/reggen/fpv_csr.sv.tpl index 66a54a5..22f8c53 100644 --- a/util/reggen/fpv_csr.sv.tpl +++ b/util/reggen/fpv_csr.sv.tpl
@@ -9,6 +9,8 @@ <% from reggen import (gen_fpv) from reggen.data import get_basename + from reggen.register import Register + from reggen.multi_register import MultiRegister from topgen import lib %>\ @@ -161,50 +163,52 @@ has_q = r.get_n_bits(["q"]) > 0 has_d = r.get_n_bits(["d"]) > 0 has_de = r.get_n_bits(["de"]) > 0 + + if isinstance(r, Register): + r0 = r + flat_regs = [r] + else: + assert isinstance(r, MultiRegister) + r0 = r.reg + flat_regs = r.regs %>\ - % if not r.shadowed: - % if r.is_multi_reg(): + % if not r0.shadowed: + % if isinstance(r, MultiRegister): <% - mreg_name = r.name + mreg_name = r0.name.lower() mreg_width_list = list() mreg_fpv_name_list = list() mreg_dut_path_list = list() mreg_has_q_list = list() mreg_has_d_list = list() mreg_has_de_list = list() - mreg_num_regs = r.get_n_fields_flat() + fields = r.get_field_list() + mreg_num_regs = len(fields) mreg_msb = -1 mreg_lsb = 0 i = 0 + + if not r.is_homogeneous(): + for field in r0.fields: + mreg_fpv_name_list.append(mreg_name + "_" + field.name.lower()) + mreg_dut_path_list.append(mreg_name + "[s]." + field.name.lower()) + mreg_width_list.append(field.bits.width()) + mreg_has_q_list.append(field.get_n_bits(r0.hwext, ["q"]) > 0) + mreg_has_d_list.append(field.get_n_bits(r0.hwext, ["d"]) > 0) + mreg_has_de_list.append(field.get_n_bits(r0.hwext, ["de"]) > 0) + mreg_num_base_fields = len(mreg_fpv_name_list) + mreg_num_regs = mreg_num_regs / mreg_num_base_fields + else: + f = fields[0] + mreg_num_base_fields = 1 + mreg_fpv_name_list.append(mreg_name) + mreg_dut_path_list.append(mreg_name + "[s]") + mreg_width_list.append(f.bits.width()) + mreg_has_q_list.append(has_q) + mreg_has_d_list.append(has_d) + mreg_has_de_list.append(has_de) %>\ - % if not r.ishomog: - % for field in r.get_reg_flat(0).fields: -<% - mreg_fpv_name_list.append(mreg_name + "_" + get_basename(field.name.lower())) - mreg_dut_path_list.append(mreg_name + "[s]." + get_basename(field.name.lower())) - mreg_width_list.append(field.bits.width()) - mreg_has_q_list.append(field.get_n_bits(r.hwext, ["q"]) > 0) - mreg_has_d_list.append(field.get_n_bits(r.hwext, ["d"]) > 0) - mreg_has_de_list.append(field.get_n_bits(r.hwext, ["de"]) > 0) -%>\ - % endfor -<% - mreg_num_base_fields = len(mreg_fpv_name_list) - mreg_num_regs = mreg_num_regs / mreg_num_base_fields -%>\ - % else: -<% - f = r.get_field_flat(0) - mreg_num_base_fields = 1 - mreg_fpv_name_list.append(mreg_name) - mreg_dut_path_list.append(mreg_name + "[s]") - mreg_width_list.append(f.bits.width()) - mreg_has_q_list.append(has_q) - mreg_has_d_list.append(has_d) - mreg_has_de_list.append(has_de) -%>\ - % endif // define local fpv variable for multi-reg % if r.get_n_bits(["q", "d"]): @@ -219,21 +223,17 @@ % endif % endif - % for reg_flat in r.get_regs_flat(): + % for reg_flat in flat_regs: <% - reg_name = reg_flat.name - reg_offset = str(reg_width) + "'h" + "%x" % reg_flat.offset - reg_msb = reg_flat.width - 1 - regwen = reg_flat.regwen + reg_name = reg_flat.name.lower() + reg_offset = "{}'h{:x}".format(reg_width, reg_flat.offset) + reg_msb = reg_flat.get_width() - 1 + reg_wen = ('`REGWEN_PATH.{}_qs'.format(reg_flat.regwen.lower()) + if reg_flat.regwen is not None else '1') reg_wr_mask = 0 %>\ - // assertions for register: ${reg_name} - % if regwen: -<% reg_wen = "`REGWEN_PATH." + regwen + "_qs" %>\ - % else: -<% reg_wen = "1" %>\ - % endif - % for f in reg_flat.get_fields_flat(): + // assertions for register: ${reg_name.lower()} + % for f in reg_flat.fields: <% field_name = f.name.lower() assert_path = reg_name + "." + field_name @@ -245,12 +245,12 @@ reg_wr_mask_h = format(reg_wr_mask, 'x') lsb = f.bits.lsb sw_rdaccess = f.swaccess.swrd().name - had_q = f.get_n_bits(r.hwext, ["q"]) > 0 - has_d = f.get_n_bits(r.hwext, ["d"]) > 0 - has_de = f.get_n_bits(r.hwext, ["de"]) > 0 + had_q = f.get_n_bits(r0.hwext, ["q"]) > 0 + has_d = f.get_n_bits(r0.hwext, ["d"]) > 0 + has_de = f.get_n_bits(r0.hwext, ["de"]) > 0 %>\ - % if not r.ishomog: - % if r.is_multi_reg(): + % if not r.is_homogeneous(): + % if isinstance(r, MultiRegister): // this is a non-homog multi-reg <% mreg_lsb = i * mreg_width_list[loop.index] @@ -262,15 +262,14 @@ % endif % endif % endfor - % if r.is_multi_reg(): <% - mreg_lsb = i * (mreg_msb - mreg_lsb + 1) - mreg_msb = mreg_lsb + reg_msb - i += 1 + if isinstance(r, MultiRegister): + mreg_lsb = i * (mreg_msb - mreg_lsb + 1) + mreg_msb = mreg_lsb + reg_msb + i += 1 %>\ - % endif - % if r.ishomog: - % if r.is_multi_reg(): + % if r.is_homogeneous(): + % if isinstance(r, MultiRegister): ${gen_multi_reg_asserts_by_category(reg_name, mreg_name, mreg_msb, mreg_lsb, reg_flat.hwext, reg_wr_mask_h)}\ % else: ${gen_asserts_by_category(reg_name, reg_name, reg_flat.hwext, reg_wr_mask_h)}\ @@ -330,7 +329,7 @@ % else: <% wr_property = "P" %>\ % endif - % if not r.ishomog: + % if not r.is_homogeneous(): <% shift_index = lsb %>\ % else: <% shift_index = 0 %>\ @@ -350,7 +349,7 @@ % else: <% rd_property = "rd_P" %>\ % endif - % if not r.ishomog: + % if not r.is_homogeneous(): <% shift_index = lsb %>\ % else: <% shift_index = 0 %>\