[verilator simutil] Add support for relative scope names to SVScoped

The SystemVerilog spec (1800-2017) doesn't seem to give any way to say
"start at the current scope and then follow the path ../../foo/bar".
Of course, it's not particularly difficult to implement once you've
decided on the semantics.

Here, we copy Python's import naming (they have the same dotted names,
so their solution should work quite well).

Suppose that the current scope is TOP.foo.bar.baz. Then SVScoped
should now resolve names as follows:

  TOP.qux -> TOP.qux
  qux     -> qux
  .       -> TOP.foo.bar.baz
  .a.b.c  -> TOP.foo.bar.baz.a.b.c
  .qux    -> TOP.foo.bar.baz.qux
  ..qux   -> TOP.foo.bar.qux
  ..      -> TOP.foo.bar
  ...     -> TOP.foo
  ....    -> TOP
  ......  -> TOP

Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
5 files changed
tree: 0f2c1991c4d302aff06d3d9f31654b027d1ed585
  1. .github/
  2. ci/
  3. doc/
  4. hw/
  5. site/
  6. sw/
  7. test/
  8. util/
  9. .clang-format
  10. .dockerignore
  11. .flake8
  12. .gitignore
  13. .style.yapf
  14. _index.md
  15. apt-requirements.txt
  16. azure-pipelines.yml
  17. check_tool_requirements.core
  18. CLA
  19. COMMITTERS
  20. CONTRIBUTING.md
  21. LICENSE
  22. meson.build
  23. meson_init.sh
  24. meson_options.txt
  25. python-requirements.txt
  26. README.md
  27. tool_requirements.py
  28. toolchain.txt
README.md

OpenTitan

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