| commit | 4c75bf9687c490f7eebc5d524c7d66a21dafcced | [log] [tgz] |
|---|---|---|
| author | Timothy Trippel <ttrippel@google.com> | Tue Mar 15 17:30:21 2022 -0700 |
| committer | Timothy Trippel <5633066+timothytrippel@users.noreply.github.com> | Wed Mar 16 21:53:24 2022 -0700 |
| tree | c79a67df975ef188773dd486bf4d1b9b62c261f7 | |
| parent | 933bb16ca024f77d40614280075a028e5741507f [diff] |
[dv] Add ROM-only chip-level test example A few chip-level tests (e.g., `chip_sw_flash_init`) must run and complete entirely in the ROM stage. This means that the conventional mechanism for running chip-level tests at the flash (ROM_EXT) stage is not suitable for such tests. This commit overcomes this by adding a mechanism to build a chip-level test to be run in ROM using the meson build system. (Conveniently, the `opentitan_functest` rule already provides such a mechanism using the `test_in_rom` rule option.) Additionally, this commit updates the DV testbench to skip loading of a flash image (either via bootstrap or via the backdoor mem util mechanism) if no such flash image is provided at runtime. Lastly, an example ROM-stage chip-level test is added to verify the correctness of the added infrastructure, and to provide a reference point for future chip-level test development. Signed-off-by: Timothy Trippel <ttrippel@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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