[top] Integrate templated pwrmgr - Also add wakeup connections, currently there is only 1 - The wakeup connection is added during the merge process, which inserts extra conections into top inter_module Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index f7d754e..a9041a4 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -329,6 +329,7 @@ } ] alert_list: [] + wakeup_list: [] scan: "false" } { @@ -377,6 +378,7 @@ } ] alert_list: [] + wakeup_list: [] scan: "false" } { @@ -502,6 +504,7 @@ } ] alert_list: [] + wakeup_list: [] scan: "true" } { @@ -603,6 +606,7 @@ } ] alert_list: [] + wakeup_list: [] scan: "false" inter_signal_list: [ @@ -651,6 +655,7 @@ } ] alert_list: [] + wakeup_list: [] scan: "false" } { @@ -678,6 +683,7 @@ available_inout_list: [] interrupt_list: [] alert_list: [] + wakeup_list: [] scan: "false" } { @@ -751,6 +757,7 @@ async: 0 } ] + wakeup_list: [] scan: "false" } { @@ -779,6 +786,7 @@ available_inout_list: [] interrupt_list: [] alert_list: [] + wakeup_list: [] scan: "false" } { @@ -811,6 +819,12 @@ available_inout_list: [] interrupt_list: [] alert_list: [] + wakeup_list: + [ + { + name: aon_wkup_req + } + ] scan: "false" inter_signal_list: [ @@ -839,6 +853,8 @@ act: req package: "" inst_name: pinmux + width: 1 + top_signame: pwrmgr_wakeups index: -1 } ] @@ -870,6 +886,7 @@ available_inout_list: [] interrupt_list: [] alert_list: [] + wakeup_list: [] scan: "false" } { @@ -954,6 +971,7 @@ } ] alert_list: [] + wakeup_list: [] scan: "false" } { @@ -971,6 +989,7 @@ rst_slow_ni: por_aon } base_addr: 0x400A0000 + generated: "true" clock_connections: { clk_i: clk_io_i @@ -998,6 +1017,7 @@ } ] alert_list: [] + wakeup_list: [] scan: "false" inter_signal_list: [ @@ -1071,11 +1091,24 @@ index: -1 } { - struct: pwr_peri + struct: logic + width: 1 type: uni - name: pwr_peri + name: wakeups act: rcv - package: pwrmgr_pkg + package: "" + inst_name: pwrmgr + top_type: broadcast + top_signame: pwrmgr_wakeups + index: -1 + } + { + struct: logic + width: 2 + type: uni + name: rstreqs + act: rcv + package: "" inst_name: pwrmgr index: -1 } @@ -1114,6 +1147,7 @@ available_inout_list: [] interrupt_list: [] alert_list: [] + wakeup_list: [] scan: "false" inter_signal_list: [ @@ -1207,6 +1241,7 @@ available_inout_list: [] interrupt_list: [] alert_list: [] + wakeup_list: [] scan: "false" inter_signal_list: [ @@ -1327,6 +1362,7 @@ } ] alert_list: [] + wakeup_list: [] scan: "false" } { @@ -1602,6 +1638,7 @@ } ] alert_list: [] + wakeup_list: [] scan: "false" inter_signal_list: [ @@ -1720,6 +1757,10 @@ [ clkmgr.pwr ] + pwrmgr.wakeups: + [ + pinmux.aon_wkup_req + ] } top: [ @@ -3219,6 +3260,10 @@ spi_device: rstmgr_resets.rst_spi_device_n usb: rstmgr_resets.rst_usb_n } + wakeups: + [ + pinmux.aon_wkup_req + ] inter_signal: { signals: @@ -3259,6 +3304,8 @@ act: req package: "" inst_name: pinmux + width: 1 + top_signame: pwrmgr_wakeups index: -1 } { @@ -3331,11 +3378,24 @@ index: -1 } { - struct: pwr_peri + struct: logic + width: 1 type: uni - name: pwr_peri + name: wakeups act: rcv - package: pwrmgr_pkg + package: "" + inst_name: pwrmgr + top_type: broadcast + top_signame: pwrmgr_wakeups + index: -1 + } + { + struct: logic + width: 2 + type: uni + name: rstreqs + act: rcv + package: "" inst_name: pwrmgr index: -1 } @@ -3508,6 +3568,13 @@ type: req_rsp } { + package: "" + struct: logic + signame: pwrmgr_wakeups + width: 1 + type: uni + } + { package: rstmgr_pkg struct: rstmgr_out signame: rstmgr_resets
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson index 07aa2b6..86c69f1 100644 --- a/hw/top_earlgrey/data/top_earlgrey.hjson +++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -212,6 +212,7 @@ clock_group: "powerup", reset_connections: {rst_ni: "por", rst_slow_ni: "por_aon"}, base_addr: "0x400A0000", + generated: "true" // Indicate this module is generated in the topgen }, { name: "rstmgr",
diff --git a/hw/top_earlgrey/ip/clkmgr/clkmgr.core b/hw/top_earlgrey/ip/clkmgr/clkmgr.core index 9e47786..5981f04 100644 --- a/hw/top_earlgrey/ip/clkmgr/clkmgr.core +++ b/hw/top_earlgrey/ip/clkmgr/clkmgr.core
@@ -11,7 +11,7 @@ - lowrisc:ip:tlul - lowrisc:prim:all - lowrisc:prim:clock_gating - - lowrisc:ip:pwrmgr + - lowrisc:ip:pwrmgr_pkg files: - rtl/autogen/clkmgr_pkg.sv - rtl/autogen/clkmgr_reg_pkg.sv
diff --git a/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson b/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson index 9577bcb..16418a6 100644 --- a/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson +++ b/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson
@@ -36,6 +36,12 @@ bus_device: "tlul", regwidth: "32", + wakeup_list: [ + { name: "aon_wkup_req", + desc: "pin wake request" + } + ], + inter_signal_list: [ // Define lc <-> pinmux signal for strap sampling { struct: "lc_pinmux_strap",
diff --git a/hw/top_earlgrey/ip/pwrmgr/data/autogen/pwrmgr.hjson b/hw/top_earlgrey/ip/pwrmgr/data/autogen/pwrmgr.hjson new file mode 100644 index 0000000..5fba2c0 --- /dev/null +++ b/hw/top_earlgrey/ip/pwrmgr/data/autogen/pwrmgr.hjson
@@ -0,0 +1,425 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ name: "PWRMGR", + clock_primary: "clk_i", + other_clock_list: [ "clk_slow_i" ] + reset_primary: "rst_ni", + other_reset_list: [ "rst_slow_ni" ] + bus_device: "tlul", + interrupt_list: [ + { name: "wakeup", desc: "Wake from low power state. See wake info for more details" }, + ], + + // Define flash_ctrl <-> flash_phy struct package + inter_signal_list: [ + { struct: "pwr_ast", + type: "req_rsp", + name: "pwr_ast", + act: "req", + package: "pwrmgr_pkg", + }, + + { struct: "pwr_rst", + type: "req_rsp", + name: "pwr_rst", + act: "req", + package: "pwrmgr_pkg", + }, + + { struct: "pwr_clk", + type: "req_rsp", + name: "pwr_clk", + act: "req", + package: "pwrmgr_pkg", + }, + + { struct: "pwr_otp", + type: "req_rsp", + name: "pwr_otp", + act: "req", + package: "pwrmgr_pkg", + }, + + { struct: "pwr_lc", + type: "req_rsp", + name: "pwr_lc", + act: "req", + package: "pwrmgr_pkg", + }, + + { struct: "pwr_flash", + type: "uni", + name: "pwr_flash", + act: "rcv", + package: "pwrmgr_pkg", + }, + + { struct: "pwr_cpu", + type: "uni", + name: "pwr_cpu", + act: "rcv", + package: "pwrmgr_pkg", + }, + + { struct: "logic", + width: 1, + type: "uni", + name: "wakeups", + act: "rcv", + package: "", + }, + + { struct: "logic", + width: 2, + type: "uni", + name: "rstreqs", + act: "rcv", + package: "", + }, + + ], + + param_list: [ + { name: "NumWkups", + desc: "Number of wakeups", + type: "int", + default: "1", + local: "true" + }, + ], + + regwidth: "32", + registers: [ + + { name: "CTRL_CFG_REGWEN", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + desc: ''' + Controls the configurability of the !!CONTROL register. + + This register ensures the contents do not change once a low power hint and + WFI has occurred. + + It unlocks whenever a low power transition has completed (transition back to the + ACTIVE state) for any reason. + ''', + + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Configuration enable. + + This bit defaults to 1 and is set to 0 by hardware when low power entry is initiated. + When the device transitions back from low power state to active state, this bit is set + back to 1 to allow software configuration of !!CONTROL + ''', + resval: "1", + }, + ] + tags: [// This regwen is completely under HW management and thus cannot be manipulated + // by software. + "excl:CsrNonInitTests:CsrExclCheck"] + }, + + + { name: "CONTROL", + desc: "Control register", + swaccess: "rw", + hwaccess: "hro", + regwen: "CTRL_CFG_REGWEN", + fields: [ + { bits: "0", + hwaccess: "hrw", + name: "LOW_POWER_HINT", + desc: ''' + The low power hint to power manager. + The hint is an indication for how the manager should treat the next WFI. + Once the power manager begins a low power transition, or if a valid reset request is registerd, + this bit is automatically cleared by HW. + ''' + resval: "0" + enum: [ + { value: "0", + name: "None", + desc: ''' + No low power intent + ''' + }, + { value: "1", + name: "Low Power", + desc: ''' + Next WFI should trigger low power entry + ''' + }, + ] + tags: [// The regwen for this reg is RO. CSR seq can't support to check this reg + "excl:CsrAllTests:CsrExclAll"] + }, + + { bits: "4", + name: "CORE_CLK_EN", + desc: "core clock enable during low power state", + resval: "0" + enum: [ + { value: "0", + name: "Disabled", + desc: ''' + Core clock disabled during low power state + ''' + }, + { value: "1", + name: "Enabled", + desc: ''' + Core clock enabled during low power state + ''' + }, + ] + }, + + { bits: "5", + name: "IO_CLK_EN", + desc: "IO clock enable during low power state", + resval: "0" + enum: [ + { value: "0", + name: "Disabled", + desc: ''' + IO clock disabled during low power state + ''' + }, + { value: "1", + name: "Enabled", + desc: ''' + IO clock enabled during low power state + ''' + }, + ] + }, + + { bits: "6", + name: "MAIN_PD_N", + desc: "Active low, main power domain power down", + resval: "1" + enum: [ + { value: "0", + name: "Power down", + desc: ''' + Main power domain is powered down during low power state. + Note this signal is active low. + ''' + }, + { value: "1", + name: "Power up", + desc: ''' + Main power domain is kept powered during low power state + Note this signal is active low. + ''' + }, + ] + }, + ], + }, + + { name: "CFG_CDC_SYNC", + swaccess: "rw", + hwaccess: "hrw", + hwqe: "true", + desc: ''' + The configuration registers CONTROL, WAKEUP_EN, RESET_EN are all written in the + fast clock domain but used in the slow clock domain. + + The configuration are not propogated across the clock boundary until this + register is triggered and read. See fields below for more details + ''', + + fields: [ + { bits: "0", + name: "SYNC", + desc: ''' + Configuration sync. When this bit is written to 1, a sync pulse is generated. When + the sync completes, this bit then self clears. + + Software should write this bit to 1, wait for it to clear, before assuming the slow clock + domain has assumed the programmaed values. + ''', + resval: "0", + }, + ] + tags: [// This bit triggers a payload synchronization and self clears when complete. + // Do not write this bit as there will be side effects and the value will not persist + "excl:CsrNonInitTests:CsrExclCheck"] + }, + + { name: "WAKEUP_EN_REGWEN", + desc: "Configuration enable for wakeup register", + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + resval: "1" + name: "EN", + desc: ''' + When 1, WAKEUP register can be configured. + When 0, WAKEUP register cannot be configured. + ''', + }, + ] + }, + + { multireg: + { name: "WAKEUP_EN", + desc: "Bit mask for enabled wakeups", + swaccess: "rw", + hwaccess: "hro", + regwen: "WAKEUP_EN_REGWEN", + resval: "0" + cname: "wakeup_en", + count: "NumWkups" + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Whenever a particular bit is set to 1, that wakeup is also enabled. + Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. + ''', + }, + ] + }, + }, + + { multireg: + { name: "WAKE_STATUS", + desc: "A read only register of all current wake requests post enable mask", + swaccess: "ro", + hwaccess: "none", + resval: "0" + cname: "wake_status", + count: "NumWkups", + fields: [ + { bits: "0", + name: "VAL", + desc: ''' + Current value of wake requests + ''', + }, + ] + }, + }, + + { name: "RESET_EN_REGWEN", + desc: "Configuration enable for reset register", + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + resval: "1" + name: "EN", + desc: ''' + When 1, RESET register can be configured. + When 0, RESET register cannot be configured. + ''', + }, + ] + }, + + { name: "RESET_EN", + desc: "Bit mask for enabled resets", + swaccess: "rw", + hwaccess: "hro", + regwen: "RESET_EN_REGWEN", + resval: "0" + fields: [ + { bits: "1:0", + name: "EN", + desc: ''' + Whenever a particular bit is set to 1, that reset request is enabled. + Whenever a particular bit is set to 0, that reset request cannot reset the device. + ''', + }, + ] + }, + + { name: "RESET_STATUS", + desc: "A read only register of all current reset requests post enable mask", + swaccess: "ro", + hwaccess: "none", + resval: "0" + fields: [ + { bits: "1:0", + name: "VAL", + desc: ''' + Current value of reset request + ''', + }, + ] + }, + + { name: "WAKE_INFO_CAPTURE_DIS", + desc: "Indicates which functions caused the chip to wakeup", + swaccess: "rw", + hwaccess: "hro", + resval: "0" + fields: [ + { bits: "0", + name: "VAL", + desc: ''' + When written to 1, this actively suppresses the wakeup info capture. + When written to 0, wakeup info capture timing is controlled by HW. + ''', + }, + ] + }, + + { name: "WAKE_INFO", + desc: ''' + Indicates which functions caused the chip to wakeup. + The wake info recording begins whenever the device begins a valid low power entry. + + This capture is continued until it is explicitly disabled through WAKE_INFO_CAPTURE_DIS. + This means it is possible to capture multiple wakeup reasons. + ''', + swaccess: "rw1c", + hwaccess: "hrw", + hwext: "true", + hwqe: "true", + resval: "0" + fields: [ + { bits: "0:0", + name: "REASONS", + desc: "Various peripheral wake reasons" + }, + { bits: "1", + name: "FALL_THROUGH", + desc: ''' + The fall through wakeup reason indicates that despite setting a WFI and providing a low power + hint, an interrupt arrived at just the right time to break the executing core out of WFI. + + The power manager detects this condition, halts low power entry and reports as a wakeup reason + ''', + }, + { bits: "2", + name: "ABORT", + desc: ''' + The abort wakeup reason indicates that despite setting a WFI and providing a low power + hint, an active flash / lifecycle / otp transaction was ongoing when the power controller + attempted to initiate low power entry. + + The power manager detects this condition, halts low power entry and reports as a wakeup reason + ''', + }, + ] + tags: [// This regwen is completely under HW management and thus cannot be manipulated + // by software. + "excl:CsrNonInitTests:CsrExclCheck"] + }, + ] +}
diff --git a/hw/top_earlgrey/ip/pwrmgr/pwrmgr_only_reg.core b/hw/top_earlgrey/ip/pwrmgr/pwrmgr_only_reg.core new file mode 100644 index 0000000..e444e27 --- /dev/null +++ b/hw/top_earlgrey/ip/pwrmgr/pwrmgr_only_reg.core
@@ -0,0 +1,20 @@ +CAPI=2: +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:top_earlgrey:pwrmgr_only_reg:0.1" +description: "Auto-generated pwrmgr register sources for top_earlgrey" + +filesets: + files_rtl: + depend: + - lowrisc:tlul:headers + files: + - rtl/autogen/pwrmgr_reg_pkg.sv + - rtl/autogen/pwrmgr_reg_top.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_rtl
diff --git a/hw/top_earlgrey/ip/pwrmgr/rtl/autogen/pwrmgr_reg_pkg.sv b/hw/top_earlgrey/ip/pwrmgr/rtl/autogen/pwrmgr_reg_pkg.sv new file mode 100644 index 0000000..f771dd3 --- /dev/null +++ b/hw/top_earlgrey/ip/pwrmgr/rtl/autogen/pwrmgr_reg_pkg.sv
@@ -0,0 +1,189 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package pwrmgr_reg_pkg; + + // Param list + parameter int NumWkups = 1; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + typedef struct packed { + logic q; + } pwrmgr_reg2hw_intr_state_reg_t; + + typedef struct packed { + logic q; + } pwrmgr_reg2hw_intr_enable_reg_t; + + typedef struct packed { + logic q; + logic qe; + } pwrmgr_reg2hw_intr_test_reg_t; + + typedef struct packed { + struct packed { + logic q; + } low_power_hint; + struct packed { + logic q; + } core_clk_en; + struct packed { + logic q; + } io_clk_en; + struct packed { + logic q; + } main_pd_n; + } pwrmgr_reg2hw_control_reg_t; + + typedef struct packed { + logic q; + logic qe; + } pwrmgr_reg2hw_cfg_cdc_sync_reg_t; + + typedef struct packed { + logic q; + } pwrmgr_reg2hw_wakeup_en_mreg_t; + + typedef struct packed { + logic [1:0] q; + } pwrmgr_reg2hw_reset_en_reg_t; + + typedef struct packed { + logic q; + } pwrmgr_reg2hw_wake_info_capture_dis_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } reasons; + struct packed { + logic q; + logic qe; + } fall_through; + struct packed { + logic q; + logic qe; + } abort; + } pwrmgr_reg2hw_wake_info_reg_t; + + + typedef struct packed { + logic d; + logic de; + } pwrmgr_hw2reg_intr_state_reg_t; + + typedef struct packed { + logic d; + } pwrmgr_hw2reg_ctrl_cfg_regwen_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } low_power_hint; + } pwrmgr_hw2reg_control_reg_t; + + typedef struct packed { + logic d; + logic de; + } pwrmgr_hw2reg_cfg_cdc_sync_reg_t; + + typedef struct packed { + struct packed { + logic d; + } reasons; + struct packed { + logic d; + } fall_through; + struct packed { + logic d; + } abort; + } pwrmgr_hw2reg_wake_info_reg_t; + + + /////////////////////////////////////// + // Register to internal design logic // + /////////////////////////////////////// + typedef struct packed { + pwrmgr_reg2hw_intr_state_reg_t intr_state; // [19:19] + pwrmgr_reg2hw_intr_enable_reg_t intr_enable; // [18:18] + pwrmgr_reg2hw_intr_test_reg_t intr_test; // [17:16] + pwrmgr_reg2hw_control_reg_t control; // [15:12] + pwrmgr_reg2hw_cfg_cdc_sync_reg_t cfg_cdc_sync; // [11:10] + pwrmgr_reg2hw_wakeup_en_mreg_t [0:0] wakeup_en; // [9:9] + pwrmgr_reg2hw_reset_en_reg_t reset_en; // [8:7] + pwrmgr_reg2hw_wake_info_capture_dis_reg_t wake_info_capture_dis; // [6:6] + pwrmgr_reg2hw_wake_info_reg_t wake_info; // [5:0] + } pwrmgr_reg2hw_t; + + /////////////////////////////////////// + // Internal design logic to register // + /////////////////////////////////////// + typedef struct packed { + pwrmgr_hw2reg_intr_state_reg_t intr_state; // [9:9] + pwrmgr_hw2reg_ctrl_cfg_regwen_reg_t ctrl_cfg_regwen; // [8:9] + pwrmgr_hw2reg_control_reg_t control; // [8:5] + pwrmgr_hw2reg_cfg_cdc_sync_reg_t cfg_cdc_sync; // [4:3] + pwrmgr_hw2reg_wake_info_reg_t wake_info; // [2:-3] + } pwrmgr_hw2reg_t; + + // Register Address + parameter logic [5:0] PWRMGR_INTR_STATE_OFFSET = 6'h 0; + parameter logic [5:0] PWRMGR_INTR_ENABLE_OFFSET = 6'h 4; + parameter logic [5:0] PWRMGR_INTR_TEST_OFFSET = 6'h 8; + parameter logic [5:0] PWRMGR_CTRL_CFG_REGWEN_OFFSET = 6'h c; + parameter logic [5:0] PWRMGR_CONTROL_OFFSET = 6'h 10; + parameter logic [5:0] PWRMGR_CFG_CDC_SYNC_OFFSET = 6'h 14; + parameter logic [5:0] PWRMGR_WAKEUP_EN_REGWEN_OFFSET = 6'h 18; + parameter logic [5:0] PWRMGR_WAKEUP_EN_OFFSET = 6'h 1c; + parameter logic [5:0] PWRMGR_WAKE_STATUS_OFFSET = 6'h 20; + parameter logic [5:0] PWRMGR_RESET_EN_REGWEN_OFFSET = 6'h 24; + parameter logic [5:0] PWRMGR_RESET_EN_OFFSET = 6'h 28; + parameter logic [5:0] PWRMGR_RESET_STATUS_OFFSET = 6'h 2c; + parameter logic [5:0] PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET = 6'h 30; + parameter logic [5:0] PWRMGR_WAKE_INFO_OFFSET = 6'h 34; + + + // Register Index + typedef enum int { + PWRMGR_INTR_STATE, + PWRMGR_INTR_ENABLE, + PWRMGR_INTR_TEST, + PWRMGR_CTRL_CFG_REGWEN, + PWRMGR_CONTROL, + PWRMGR_CFG_CDC_SYNC, + PWRMGR_WAKEUP_EN_REGWEN, + PWRMGR_WAKEUP_EN, + PWRMGR_WAKE_STATUS, + PWRMGR_RESET_EN_REGWEN, + PWRMGR_RESET_EN, + PWRMGR_RESET_STATUS, + PWRMGR_WAKE_INFO_CAPTURE_DIS, + PWRMGR_WAKE_INFO + } pwrmgr_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] PWRMGR_PERMIT [14] = '{ + 4'b 0001, // index[ 0] PWRMGR_INTR_STATE + 4'b 0001, // index[ 1] PWRMGR_INTR_ENABLE + 4'b 0001, // index[ 2] PWRMGR_INTR_TEST + 4'b 0001, // index[ 3] PWRMGR_CTRL_CFG_REGWEN + 4'b 0001, // index[ 4] PWRMGR_CONTROL + 4'b 0001, // index[ 5] PWRMGR_CFG_CDC_SYNC + 4'b 0001, // index[ 6] PWRMGR_WAKEUP_EN_REGWEN + 4'b 0001, // index[ 7] PWRMGR_WAKEUP_EN + 4'b 0001, // index[ 8] PWRMGR_WAKE_STATUS + 4'b 0001, // index[ 9] PWRMGR_RESET_EN_REGWEN + 4'b 0001, // index[10] PWRMGR_RESET_EN + 4'b 0001, // index[11] PWRMGR_RESET_STATUS + 4'b 0001, // index[12] PWRMGR_WAKE_INFO_CAPTURE_DIS + 4'b 0001 // index[13] PWRMGR_WAKE_INFO + }; +endpackage +
diff --git a/hw/top_earlgrey/ip/pwrmgr/rtl/autogen/pwrmgr_reg_top.sv b/hw/top_earlgrey/ip/pwrmgr/rtl/autogen/pwrmgr_reg_top.sv new file mode 100644 index 0000000..2365da5 --- /dev/null +++ b/hw/top_earlgrey/ip/pwrmgr/rtl/autogen/pwrmgr_reg_top.sv
@@ -0,0 +1,727 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + +`include "prim_assert.sv" + +module pwrmgr_reg_top ( + input clk_i, + input rst_ni, + + // Below Regster interface can be changed + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // To HW + output pwrmgr_reg_pkg::pwrmgr_reg2hw_t reg2hw, // Write + input pwrmgr_reg_pkg::pwrmgr_hw2reg_t hw2reg, // Read + + // Config + input devmode_i // If 1, explicit error return for unmapped register access +); + + import pwrmgr_reg_pkg::* ; + + localparam int AW = 6; + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + + tlul_pkg::tl_h2d_t tl_reg_h2d; + tlul_pkg::tl_d2h_t tl_reg_d2h; + + assign tl_reg_h2d = tl_i; + assign tl_o = tl_reg_d2h; + + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW) + ) u_reg_if ( + .clk_i, + .rst_ni, + + .tl_i (tl_reg_h2d), + .tl_o (tl_reg_d2h), + + .we_o (reg_we), + .re_o (reg_re), + .addr_o (reg_addr), + .wdata_o (reg_wdata), + .be_o (reg_be), + .rdata_i (reg_rdata), + .error_i (reg_error) + ); + + assign reg_rdata = reg_rdata_next ; + assign reg_error = (devmode_i & addrmiss) | wr_err ; + + // Define SW related signals + // Format: <reg>_<field>_{wd|we|qs} + // or <reg>_{wd|we|qs} if field == 1 or 0 + logic intr_state_qs; + logic intr_state_wd; + logic intr_state_we; + logic intr_enable_qs; + logic intr_enable_wd; + logic intr_enable_we; + logic intr_test_wd; + logic intr_test_we; + logic ctrl_cfg_regwen_qs; + logic ctrl_cfg_regwen_re; + logic control_low_power_hint_qs; + logic control_low_power_hint_wd; + logic control_low_power_hint_we; + logic control_core_clk_en_qs; + logic control_core_clk_en_wd; + logic control_core_clk_en_we; + logic control_io_clk_en_qs; + logic control_io_clk_en_wd; + logic control_io_clk_en_we; + logic control_main_pd_n_qs; + logic control_main_pd_n_wd; + logic control_main_pd_n_we; + logic cfg_cdc_sync_qs; + logic cfg_cdc_sync_wd; + logic cfg_cdc_sync_we; + logic wakeup_en_regwen_qs; + logic wakeup_en_regwen_wd; + logic wakeup_en_regwen_we; + logic wakeup_en_qs; + logic wakeup_en_wd; + logic wakeup_en_we; + logic wake_status_qs; + logic reset_en_regwen_qs; + logic reset_en_regwen_wd; + logic reset_en_regwen_we; + logic [1:0] reset_en_qs; + logic [1:0] reset_en_wd; + logic reset_en_we; + logic [1:0] reset_status_qs; + logic wake_info_capture_dis_qs; + logic wake_info_capture_dis_wd; + logic wake_info_capture_dis_we; + logic wake_info_reasons_qs; + logic wake_info_reasons_wd; + logic wake_info_reasons_we; + logic wake_info_reasons_re; + logic wake_info_fall_through_qs; + logic wake_info_fall_through_wd; + logic wake_info_fall_through_we; + logic wake_info_fall_through_re; + logic wake_info_abort_qs; + logic wake_info_abort_wd; + logic wake_info_abort_we; + logic wake_info_abort_re; + + // Register instances + // R[intr_state]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intr_state ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intr_state_we), + .wd (intr_state_wd), + + // from internal hardware + .de (hw2reg.intr_state.de), + .d (hw2reg.intr_state.d ), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.q ), + + // to register interface (read) + .qs (intr_state_qs) + ); + + + // R[intr_enable]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intr_enable ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.q ), + + // to register interface (read) + .qs (intr_enable_qs) + ); + + + // R[intr_test]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_intr_test ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_wd), + .d ('0), + .qre (), + .qe (reg2hw.intr_test.qe), + .q (reg2hw.intr_test.q ), + .qs () + ); + + + // R[ctrl_cfg_regwen]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_ctrl_cfg_regwen ( + .re (ctrl_cfg_regwen_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.ctrl_cfg_regwen.d), + .qre (), + .qe (), + .q (), + .qs (ctrl_cfg_regwen_qs) + ); + + + // R[control]: V(False) + + // F[low_power_hint]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_control_low_power_hint ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (control_low_power_hint_we & ctrl_cfg_regwen_qs), + .wd (control_low_power_hint_wd), + + // from internal hardware + .de (hw2reg.control.low_power_hint.de), + .d (hw2reg.control.low_power_hint.d ), + + // to internal hardware + .qe (), + .q (reg2hw.control.low_power_hint.q ), + + // to register interface (read) + .qs (control_low_power_hint_qs) + ); + + + // F[core_clk_en]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_control_core_clk_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (control_core_clk_en_we & ctrl_cfg_regwen_qs), + .wd (control_core_clk_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.control.core_clk_en.q ), + + // to register interface (read) + .qs (control_core_clk_en_qs) + ); + + + // F[io_clk_en]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_control_io_clk_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (control_io_clk_en_we & ctrl_cfg_regwen_qs), + .wd (control_io_clk_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.control.io_clk_en.q ), + + // to register interface (read) + .qs (control_io_clk_en_qs) + ); + + + // F[main_pd_n]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_control_main_pd_n ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (control_main_pd_n_we & ctrl_cfg_regwen_qs), + .wd (control_main_pd_n_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.control.main_pd_n.q ), + + // to register interface (read) + .qs (control_main_pd_n_qs) + ); + + + // R[cfg_cdc_sync]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_cfg_cdc_sync ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_cdc_sync_we), + .wd (cfg_cdc_sync_wd), + + // from internal hardware + .de (hw2reg.cfg_cdc_sync.de), + .d (hw2reg.cfg_cdc_sync.d ), + + // to internal hardware + .qe (reg2hw.cfg_cdc_sync.qe), + .q (reg2hw.cfg_cdc_sync.q ), + + // to register interface (read) + .qs (cfg_cdc_sync_qs) + ); + + + // R[wakeup_en_regwen]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_wakeup_en_regwen ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wakeup_en_regwen_we), + .wd (wakeup_en_regwen_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (wakeup_en_regwen_qs) + ); + + + + // Subregister 0 of Multireg wakeup_en + // R[wakeup_en]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_wakeup_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (wakeup_en_we & wakeup_en_regwen_qs), + .wd (wakeup_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.wakeup_en[0].q ), + + // to register interface (read) + .qs (wakeup_en_qs) + ); + + + + // Subregister 0 of Multireg wake_status + // R[wake_status]: V(False) + + // constant-only read + assign wake_status_qs = 1'h0; + + + // R[reset_en_regwen]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_reset_en_regwen ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (reset_en_regwen_we), + .wd (reset_en_regwen_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (reset_en_regwen_qs) + ); + + + // R[reset_en]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_reset_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (reset_en_we & reset_en_regwen_qs), + .wd (reset_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.reset_en.q ), + + // to register interface (read) + .qs (reset_en_qs) + ); + + + // R[reset_status]: V(False) + + // constant-only read + assign reset_status_qs = 2'h0; + + + // R[wake_info_capture_dis]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_wake_info_capture_dis ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (wake_info_capture_dis_we), + .wd (wake_info_capture_dis_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.wake_info_capture_dis.q ), + + // to register interface (read) + .qs (wake_info_capture_dis_qs) + ); + + + // R[wake_info]: V(True) + + // F[reasons]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_wake_info_reasons ( + .re (wake_info_reasons_re), + .we (wake_info_reasons_we), + .wd (wake_info_reasons_wd), + .d (hw2reg.wake_info.reasons.d), + .qre (), + .qe (reg2hw.wake_info.reasons.qe), + .q (reg2hw.wake_info.reasons.q ), + .qs (wake_info_reasons_qs) + ); + + + // F[fall_through]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_wake_info_fall_through ( + .re (wake_info_fall_through_re), + .we (wake_info_fall_through_we), + .wd (wake_info_fall_through_wd), + .d (hw2reg.wake_info.fall_through.d), + .qre (), + .qe (reg2hw.wake_info.fall_through.qe), + .q (reg2hw.wake_info.fall_through.q ), + .qs (wake_info_fall_through_qs) + ); + + + // F[abort]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_wake_info_abort ( + .re (wake_info_abort_re), + .we (wake_info_abort_we), + .wd (wake_info_abort_wd), + .d (hw2reg.wake_info.abort.d), + .qre (), + .qe (reg2hw.wake_info.abort.qe), + .q (reg2hw.wake_info.abort.q ), + .qs (wake_info_abort_qs) + ); + + + + + logic [13:0] addr_hit; + always_comb begin + addr_hit = '0; + addr_hit[ 0] = (reg_addr == PWRMGR_INTR_STATE_OFFSET); + addr_hit[ 1] = (reg_addr == PWRMGR_INTR_ENABLE_OFFSET); + addr_hit[ 2] = (reg_addr == PWRMGR_INTR_TEST_OFFSET); + addr_hit[ 3] = (reg_addr == PWRMGR_CTRL_CFG_REGWEN_OFFSET); + addr_hit[ 4] = (reg_addr == PWRMGR_CONTROL_OFFSET); + addr_hit[ 5] = (reg_addr == PWRMGR_CFG_CDC_SYNC_OFFSET); + addr_hit[ 6] = (reg_addr == PWRMGR_WAKEUP_EN_REGWEN_OFFSET); + addr_hit[ 7] = (reg_addr == PWRMGR_WAKEUP_EN_OFFSET); + addr_hit[ 8] = (reg_addr == PWRMGR_WAKE_STATUS_OFFSET); + addr_hit[ 9] = (reg_addr == PWRMGR_RESET_EN_REGWEN_OFFSET); + addr_hit[10] = (reg_addr == PWRMGR_RESET_EN_OFFSET); + addr_hit[11] = (reg_addr == PWRMGR_RESET_STATUS_OFFSET); + addr_hit[12] = (reg_addr == PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET); + addr_hit[13] = (reg_addr == PWRMGR_WAKE_INFO_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = 1'b0; + if (addr_hit[ 0] && reg_we && (PWRMGR_PERMIT[ 0] != (PWRMGR_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[ 1] && reg_we && (PWRMGR_PERMIT[ 1] != (PWRMGR_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[ 2] && reg_we && (PWRMGR_PERMIT[ 2] != (PWRMGR_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[ 3] && reg_we && (PWRMGR_PERMIT[ 3] != (PWRMGR_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[ 4] && reg_we && (PWRMGR_PERMIT[ 4] != (PWRMGR_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[ 5] && reg_we && (PWRMGR_PERMIT[ 5] != (PWRMGR_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[ 6] && reg_we && (PWRMGR_PERMIT[ 6] != (PWRMGR_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[ 7] && reg_we && (PWRMGR_PERMIT[ 7] != (PWRMGR_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[ 8] && reg_we && (PWRMGR_PERMIT[ 8] != (PWRMGR_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[ 9] && reg_we && (PWRMGR_PERMIT[ 9] != (PWRMGR_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[10] && reg_we && (PWRMGR_PERMIT[10] != (PWRMGR_PERMIT[10] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[11] && reg_we && (PWRMGR_PERMIT[11] != (PWRMGR_PERMIT[11] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[12] && reg_we && (PWRMGR_PERMIT[12] != (PWRMGR_PERMIT[12] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[13] && reg_we && (PWRMGR_PERMIT[13] != (PWRMGR_PERMIT[13] & reg_be))) wr_err = 1'b1 ; + end + + assign intr_state_we = addr_hit[0] & reg_we & ~wr_err; + assign intr_state_wd = reg_wdata[0]; + + assign intr_enable_we = addr_hit[1] & reg_we & ~wr_err; + assign intr_enable_wd = reg_wdata[0]; + + assign intr_test_we = addr_hit[2] & reg_we & ~wr_err; + assign intr_test_wd = reg_wdata[0]; + + assign ctrl_cfg_regwen_re = addr_hit[3] && reg_re; + + assign control_low_power_hint_we = addr_hit[4] & reg_we & ~wr_err; + assign control_low_power_hint_wd = reg_wdata[0]; + + assign control_core_clk_en_we = addr_hit[4] & reg_we & ~wr_err; + assign control_core_clk_en_wd = reg_wdata[4]; + + assign control_io_clk_en_we = addr_hit[4] & reg_we & ~wr_err; + assign control_io_clk_en_wd = reg_wdata[5]; + + assign control_main_pd_n_we = addr_hit[4] & reg_we & ~wr_err; + assign control_main_pd_n_wd = reg_wdata[6]; + + assign cfg_cdc_sync_we = addr_hit[5] & reg_we & ~wr_err; + assign cfg_cdc_sync_wd = reg_wdata[0]; + + assign wakeup_en_regwen_we = addr_hit[6] & reg_we & ~wr_err; + assign wakeup_en_regwen_wd = reg_wdata[0]; + + assign wakeup_en_we = addr_hit[7] & reg_we & ~wr_err; + assign wakeup_en_wd = reg_wdata[0]; + + + assign reset_en_regwen_we = addr_hit[9] & reg_we & ~wr_err; + assign reset_en_regwen_wd = reg_wdata[0]; + + assign reset_en_we = addr_hit[10] & reg_we & ~wr_err; + assign reset_en_wd = reg_wdata[1:0]; + + + assign wake_info_capture_dis_we = addr_hit[12] & reg_we & ~wr_err; + assign wake_info_capture_dis_wd = reg_wdata[0]; + + assign wake_info_reasons_we = addr_hit[13] & reg_we & ~wr_err; + assign wake_info_reasons_wd = reg_wdata[0]; + assign wake_info_reasons_re = addr_hit[13] && reg_re; + + assign wake_info_fall_through_we = addr_hit[13] & reg_we & ~wr_err; + assign wake_info_fall_through_wd = reg_wdata[1]; + assign wake_info_fall_through_re = addr_hit[13] && reg_re; + + assign wake_info_abort_we = addr_hit[13] & reg_we & ~wr_err; + assign wake_info_abort_wd = reg_wdata[2]; + assign wake_info_abort_re = addr_hit[13] && reg_re; + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[0] = intr_state_qs; + end + + addr_hit[1]: begin + reg_rdata_next[0] = intr_enable_qs; + end + + addr_hit[2]: begin + reg_rdata_next[0] = '0; + end + + addr_hit[3]: begin + reg_rdata_next[0] = ctrl_cfg_regwen_qs; + end + + addr_hit[4]: begin + reg_rdata_next[0] = control_low_power_hint_qs; + reg_rdata_next[4] = control_core_clk_en_qs; + reg_rdata_next[5] = control_io_clk_en_qs; + reg_rdata_next[6] = control_main_pd_n_qs; + end + + addr_hit[5]: begin + reg_rdata_next[0] = cfg_cdc_sync_qs; + end + + addr_hit[6]: begin + reg_rdata_next[0] = wakeup_en_regwen_qs; + end + + addr_hit[7]: begin + reg_rdata_next[0] = wakeup_en_qs; + end + + addr_hit[8]: begin + reg_rdata_next[0] = wake_status_qs; + end + + addr_hit[9]: begin + reg_rdata_next[0] = reset_en_regwen_qs; + end + + addr_hit[10]: begin + reg_rdata_next[1:0] = reset_en_qs; + end + + addr_hit[11]: begin + reg_rdata_next[1:0] = reset_status_qs; + end + + addr_hit[12]: begin + reg_rdata_next[0] = wake_info_capture_dis_qs; + end + + addr_hit[13]: begin + reg_rdata_next[0] = wake_info_reasons_qs; + reg_rdata_next[1] = wake_info_fall_through_qs; + reg_rdata_next[2] = wake_info_abort_qs; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // Assertions for Register Interface + `ASSERT_PULSE(wePulse, reg_we) + `ASSERT_PULSE(rePulse, reg_re) + + `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid) + + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit)) + + // this is formulated as an assumption such that the FPV testbenches do disprove this + // property by mistake + `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0) + +endmodule
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index 4ef2db9..ee03429 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -250,6 +250,7 @@ pwrmgr_pkg::pwr_rst_rsp_t pwrmgr_pwr_rst_rsp; pwrmgr_pkg::pwr_clk_req_t pwrmgr_pwr_clk_req; pwrmgr_pkg::pwr_clk_rsp_t pwrmgr_pwr_clk_rsp; + logic pwrmgr_wakeups; rstmgr_pkg::rstmgr_out_t rstmgr_resets; rstmgr_pkg::rstmgr_cpu_t rstmgr_cpu; pwrmgr_pkg::pwr_cpu_t pwrmgr_pwr_cpu; @@ -627,8 +628,8 @@ // Inter-module signals .lc_pinmux_strap_i(pinmux_pkg::LC_PINMUX_STRAP_REQ_DEFAULT), .lc_pinmux_strap_o(), - .sleep_en_i(1'b0), - .aon_wkup_req_o(), + .sleep_en_i('0), + .aon_wkup_req_o(pwrmgr_wakeups), .periph_to_mio_i (mio_d2p ), .periph_to_mio_oe_i (mio_d2p_en ), @@ -707,7 +708,8 @@ .pwr_lc_i(pwrmgr_pkg::PWR_LC_RSP_DEFAULT), .pwr_flash_i(pwrmgr_pkg::PWR_FLASH_DEFAULT), .pwr_cpu_i(pwrmgr_pwr_cpu), - .pwr_peri_i(pwrmgr_pkg::PWR_PERI_DEFAULT), + .wakeups_i(pwrmgr_wakeups), + .rstreqs_i('0), .clk_i (clk_io_i), .clk_slow_i (clk_aon_i),
diff --git a/hw/top_earlgrey/top_earlgrey.core b/hw/top_earlgrey/top_earlgrey.core index 891c388..fa47f83 100644 --- a/hw/top_earlgrey/top_earlgrey.core +++ b/hw/top_earlgrey/top_earlgrey.core
@@ -24,7 +24,6 @@ - lowrisc:ip:spi_device - lowrisc:ip:aes - lowrisc:ip:hmac - - lowrisc:ip:pwrmgr - lowrisc:prim:ram_1p_adv - lowrisc:prim:rom_adv - lowrisc:ip:rstmgr @@ -36,6 +35,9 @@ - lowrisc:top_earlgrey:xbar_main - lowrisc:top_earlgrey:xbar_peri - lowrisc:ip:rstmgr + - lowrisc:top_earlgrey:pwrmgr_only_reg + - lowrisc:ip:pwrmgr_pkg + - lowrisc:ip:pwrmgr_component - lowrisc:tlul:headers - lowrisc:prim:all files: