[rv_core_ibex] Make use of tlul_adapter_host
rv_core_ibex had its own adapter logic to connect Ibex to TL-UL. This
uses the tlul_adapter_host module instead.
Signed-off-by: Greg Chadwick <gac@lowrisc.org>
diff --git a/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv b/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv
index 90edc6a..9cc2091 100644
--- a/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv
+++ b/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv
@@ -60,25 +60,25 @@
// if pipeline is 0, passthrough the fifo completely
localparam int FifoPass = PipeLine ? 1'b0 : 1'b1;
localparam int FifoDepth = PipeLine ? 4'h2 : 4'h0;
- localparam int WordSize = $clog2(TL_DW / 8);
- // Inst interface (internal)
- logic instr_req_o;
- logic instr_gnt_i;
- logic instr_rvalid_i;
- logic [31:0] instr_addr_o;
- logic [31:0] instr_rdata_i;
- logic instr_err_i;
+ // Instruction interface (internal)
+ logic instr_req;
+ logic instr_gnt;
+ logic instr_rvalid;
+ logic [31:0] instr_addr;
+ logic [31:0] instr_rdata;
+ logic instr_err;
- logic data_req_o;
- logic data_gnt_i;
- logic data_rvalid_i;
- logic data_we_o;
- logic [3:0] data_be_o;
- logic [31:0] data_addr_o;
- logic [31:0] data_wdata_o;
- logic [31:0] data_rdata_i;
- logic data_err_i;
+ // Data interface (internal)
+ logic data_req;
+ logic data_gnt;
+ logic data_rvalid;
+ logic data_we;
+ logic [3:0] data_be;
+ logic [31:0] data_addr;
+ logic [31:0] data_wdata;
+ logic [31:0] data_rdata;
+ logic data_err;
// Pipeline interfaces
tl_h2d_t tl_i_ibex2fifo;
@@ -129,22 +129,22 @@
.hart_id_i,
.boot_addr_i,
- .instr_req_o,
- .instr_gnt_i,
- .instr_rvalid_i,
- .instr_addr_o,
- .instr_rdata_i,
- .instr_err_i,
+ .instr_req_o ( instr_req ),
+ .instr_gnt_i ( instr_gnt ),
+ .instr_rvalid_i ( instr_rvalid ),
+ .instr_addr_o ( instr_addr ),
+ .instr_rdata_i ( instr_rdata ),
+ .instr_err_i ( instr_err ),
- .data_req_o,
- .data_gnt_i,
- .data_rvalid_i,
- .data_we_o,
- .data_be_o,
- .data_addr_o,
- .data_wdata_o,
- .data_rdata_i,
- .data_err_i,
+ .data_req_o ( data_req ),
+ .data_gnt_i ( data_gnt ),
+ .data_rvalid_i ( data_rvalid ),
+ .data_we_o ( data_we ),
+ .data_be_o ( data_be ),
+ .data_addr_o ( data_addr ),
+ .data_wdata_o ( data_wdata ),
+ .data_rdata_i ( data_rdata ),
+ .data_err_i ( data_err ),
.irq_software_i,
.irq_timer_i,
@@ -185,37 +185,23 @@
// Convert ibex data/instruction bus to TL-UL
//
- // Generate a_source fields by toggling between 0 and 1
- logic tl_i_source, tl_d_source;
- always_ff @(posedge clk_i or negedge rst_ni) begin
- if (!rst_ni) begin
- {tl_i_source, tl_d_source} <= '0;
- end else begin
- if (instr_req_o && instr_gnt_i) tl_i_source <= !tl_i_source;
- if (data_req_o && data_gnt_i) tl_d_source <= !tl_d_source;
- end
- end
-
- // Convert core instruction interface to TL-UL
- // The outgoing address is always word aligned
- assign tl_i_ibex2fifo = '{
- a_valid: instr_req_o,
- a_opcode: tlul_pkg::Get,
- a_param: 3'h0,
- a_size: 2'(WordSize),
- a_mask: {TL_DBW{1'b1}},
- a_source: TL_AIW'(tl_i_source),
- a_address: {instr_addr_o[31:WordSize], {WordSize{1'b0}}},
- a_data: {TL_DW{1'b0}},
- a_user: '{default:'0},
-
- d_ready: 1'b1
- };
-
- assign instr_gnt_i = tl_i_fifo2ibex.a_ready & tl_i_ibex2fifo.a_valid;
- assign instr_rvalid_i = tl_i_fifo2ibex.d_valid;
- assign instr_rdata_i = tl_i_fifo2ibex.d_data;
- assign instr_err_i = tl_i_fifo2ibex.d_error;
+ tlul_adapter_host #(
+ .MAX_REQS(2)
+ ) tl_adapter_host_i_ibex (
+ .clk_i,
+ .rst_ni,
+ .req_i (instr_req),
+ .gnt_o (instr_gnt),
+ .addr_i (instr_addr),
+ .we_i (1'b0),
+ .wdata_i (32'b0),
+ .be_i (4'hF),
+ .valid_o (instr_rvalid),
+ .rdata_o (instr_rdata),
+ .err_o (instr_err),
+ .tl_o (tl_i_ibex2fifo),
+ .tl_i (tl_i_fifo2ibex)
+ );
tlul_fifo_sync #(
.ReqPass(FifoPass),
@@ -234,30 +220,23 @@
.spare_rsp_i (1'b0),
.spare_rsp_o ());
- // Convert core data interface to TL-UL
- // The outgoing address is always word aligned. If it's a write access that occupies
- // all lanes, then the operation is always PutFullData; otherwise it is always PutPartialData
- // When in partial opertaion, tlul allows writes smaller than the operation size, thus
- // size / mask information can be directly passed through
- assign tl_d_ibex2fifo = '{
- a_valid: data_req_o,
- a_opcode: (~data_we_o) ? tlul_pkg::Get :
- (data_be_o == 4'hf) ? tlul_pkg::PutFullData :
- tlul_pkg::PutPartialData,
- a_param: 3'h0,
- a_size: 2'(WordSize),
- a_mask: data_be_o,
- a_source: TL_AIW'(tl_d_source),
- a_address: {data_addr_o[31:WordSize], {WordSize{1'b0}}},
- a_data: data_wdata_o,
- a_user: '{default:'0},
-
- d_ready: 1'b1
- };
- assign data_gnt_i = tl_d_fifo2ibex.a_ready & tl_d_ibex2fifo.a_valid;
- assign data_rvalid_i = tl_d_fifo2ibex.d_valid;
- assign data_rdata_i = tl_d_fifo2ibex.d_data;
- assign data_err_i = tl_d_fifo2ibex.d_error;
+ tlul_adapter_host #(
+ .MAX_REQS(2)
+ ) tl_adapter_host_d_ibex (
+ .clk_i,
+ .rst_ni,
+ .req_i (data_req),
+ .gnt_o (data_gnt),
+ .addr_i (data_addr),
+ .we_i (data_we),
+ .wdata_i (data_wdata),
+ .be_i (data_be),
+ .valid_o (data_rvalid),
+ .rdata_o (data_rdata),
+ .err_o (data_err),
+ .tl_o (tl_d_ibex2fifo),
+ .tl_i (tl_d_fifo2ibex)
+ );
tlul_fifo_sync #(
.ReqPass(FifoPass),
diff --git a/hw/ip/rv_core_ibex/rv_core_ibex.core b/hw/ip/rv_core_ibex/rv_core_ibex.core
index a047d10..2a7e642 100644
--- a/hw/ip/rv_core_ibex/rv_core_ibex.core
+++ b/hw/ip/rv_core_ibex/rv_core_ibex.core
@@ -11,6 +11,7 @@
- lowrisc:prim:all
- lowrisc:prim:clock_gating
- lowrisc:ip:tlul
+ - lowrisc:tlul:adapter_host
files:
- rtl/rv_core_ibex.sv
file_type: systemVerilogSource
