[otbn] Tidy up long lines and unnecessary imports in Python code
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
diff --git a/hw/ip/otbn/dv/otbnsim/sim/sim.py b/hw/ip/otbn/dv/otbnsim/sim/sim.py
index 20bac52..134b1e5 100644
--- a/hw/ip/otbn/dv/otbnsim/sim/sim.py
+++ b/hw/ip/otbn/dv/otbnsim/sim/sim.py
@@ -137,7 +137,8 @@
# cycle after that until we start executing instructions, but that
# doesn't really matter)
changes = self._on_stall(verbose, fetch_next=False)
- changes += [TraceExtRegChange('RND_REQ', ExtRegChange('=', 0, True, 0))]
+ changes += [TraceExtRegChange('RND_REQ',
+ ExtRegChange('=', 0, True, 0))]
self.state.ext_regs.write('INSN_CNT', 0, True)
return (None, changes)
diff --git a/hw/ip/otbn/dv/otbnsim/sim/standalonesim.py b/hw/ip/otbn/dv/otbnsim/sim/standalonesim.py
index 36bbd91..3fef649 100644
--- a/hw/ip/otbn/dv/otbnsim/sim/standalonesim.py
+++ b/hw/ip/otbn/dv/otbnsim/sim/standalonesim.py
@@ -9,8 +9,10 @@
# This is the default seed for URND PRNG. Note that the actualy URND value will
# be random since we are modelling PRNG inside the URND register model.
-_TEST_URND_DATA = \
- [0x84ddfadaf7e1134d, 0x70aa1c59de6197ff, 0x25a4fe335d095f1e, 0x2cba89acbe4a07e9]
+_TEST_URND_DATA = [
+ 0x84ddfadaf7e1134d, 0x70aa1c59de6197ff,
+ 0x25a4fe335d095f1e, 0x2cba89acbe4a07e9
+]
class StandaloneSim(OTBNSim):
diff --git a/hw/ip/otbn/dv/otbnsim/sim/state.py b/hw/ip/otbn/dv/otbnsim/sim/state.py
index b92bb7a..e49a8df 100644
--- a/hw/ip/otbn/dv/otbnsim/sim/state.py
+++ b/hw/ip/otbn/dv/otbnsim/sim/state.py
@@ -40,7 +40,7 @@
there has been a fatal error. It matches Status.LOCKED.
PRE_EXEC, FETCH_WAIT, EXEC, POST_EXEC and LOCKING correspond to
- Status.BUSY_EXECUTE. PRE_EXEC is the period after starting OTBN where we're
+ Status.BUSY_EXECUTE. PRE_EXEC is the period after starting OTBN where we're
still waiting for an EDN value to seed URND. FETCH_WAIT is the single cycle
delay after seeding URND to fill the prefetch stage. EXEC is the period
where we start fetching and executing instructions.
diff --git a/hw/ip/otbn/dv/otbnsim/sim/wsr.py b/hw/ip/otbn/dv/otbnsim/sim/wsr.py
index b53664f..122c633 100644
--- a/hw/ip/otbn/dv/otbnsim/sim/wsr.py
+++ b/hw/ip/otbn/dv/otbnsim/sim/wsr.py
@@ -184,8 +184,8 @@
self._value = None # type: Optional[int]
self.running = False
- # Function to left rotate a 64b number n by d bits
- def leftRotate64(self, n: int, d: int) -> int:
+ def rol(self, n: int, d: int) -> int:
+ '''Rotate n left by d bits'''
return ((n << d) & ((1 << 64) - 1)) | (n >> (64 - d))
def read_u32(self) -> int:
@@ -209,7 +209,7 @@
a_out = a_in ^ b_in ^ d_in
b_out = a_in ^ b_in ^ c_in
c_out = a_in ^ ((b_in << 17) & ((1 << 64) - 1)) ^ c_in
- d_out = self.leftRotate64(d_in, 45) ^ self.leftRotate64(b_in, 45)
+ d_out = self.rol(d_in, 45) ^ self.rol(b_in, 45)
assert a_out < (1 << 64)
assert b_out < (1 << 64)
assert c_out < (1 << 64)
@@ -222,13 +222,16 @@
def step(self) -> None:
if self.running:
+ mask64 = (1 << 64) - 1
mid = 4 * [0]
- self._next_value = 0
+ nv = 0
for i in range(4):
- self.state[i + 1] = self.state_update(self.state[i])
- mid[i] = (self.state[i][3] + self.state[i][0]) & ((1 << 64) - 1)
- self.out[i] = (self.leftRotate64(mid[i], 23) + self.state[i][3]) & ((1 << 64) - 1)
- self._next_value = (self._next_value | (self.out[i] << (64 * i))) & ((1 << 256) - 1)
+ st_i = self.state[i]
+ self.state[i + 1] = self.state_update(st_i)
+ mid[i] = (st_i[3] + st_i[0]) & mask64
+ self.out[i] = (self.rol(mid[i], 23) + st_i[3]) & mask64
+ nv |= self.out[i] << (64 * i)
+ self._next_value = nv
self.state[0] = self.state[4]
def commit(self) -> None:
diff --git a/hw/ip/otbn/dv/otbnsim/stepped.py b/hw/ip/otbn/dv/otbnsim/stepped.py
index 208fcf8..edfd96a 100755
--- a/hw/ip/otbn/dv/otbnsim/stepped.py
+++ b/hw/ip/otbn/dv/otbnsim/stepped.py
@@ -50,8 +50,8 @@
is also finished processing 32b packages from EDN and
set the seed.
- edn_flush Flush EDN data from model because of reset signal in EDN
- CLOCK DOMAIN
+ edn_flush Flush EDN data from model because of reset signal in
+ EDN clock domain
invalidate_imem Mark all of IMEM as having invalid ECC checksums
diff --git a/hw/ip/otbn/util/check_call_stack.py b/hw/ip/otbn/util/check_call_stack.py
index c063162..f59cb7a 100755
--- a/hw/ip/otbn/util/check_call_stack.py
+++ b/hw/ip/otbn/util/check_call_stack.py
@@ -5,7 +5,7 @@
import argparse
import sys
-from typing import Dict, Tuple
+from typing import Dict
from shared.check import CheckResult
from shared.decode import OTBNProgram, decode_elf
diff --git a/hw/ip/otbn/util/check_loop.py b/hw/ip/otbn/util/check_loop.py
index e5b44f1..01b1071 100755
--- a/hw/ip/otbn/util/check_loop.py
+++ b/hw/ip/otbn/util/check_loop.py
@@ -5,11 +5,10 @@
import argparse
import sys
-from typing import Dict, List, Tuple
+from typing import List
from shared.check import CheckResult
from shared.decode import OTBNProgram, decode_elf
-from shared.insn_yaml import Insn
class CodeSection:
@@ -30,7 +29,7 @@
def _get_pcs_for_mnemonics(program: OTBNProgram,
mnems: List[str]) -> List[int]:
- '''Gets all PCs in the program at which the given instruction is present.'''
+ '''Gets all PCs in the program holding the given instruction.'''
return [
pc for (pc, (insn, _)) in program.insns.items()
if insn.mnemonic in mnems
@@ -52,7 +51,6 @@
loop_starts = _get_loop_starts(program)
loops = []
for pc in loop_starts:
- insn = program.get_insn(pc)
operands = program.get_operands(pc)
end_pc = pc + operands['bodysize'] * 4
loops.append(CodeSection(pc + 4, end_pc))
@@ -63,10 +61,11 @@
loops: List[CodeSection]) -> CheckResult:
'''Checks number of iterations for loopi.
- If the number of iterations is 0, this check fails; `loopi` requires at least
- one iteration and will raise a LOOP error otherwise. The `loop` instruction
- also has this requirement, but since the number of loop iterations comes
- from a register it's harder to check statically and is not considered here.
+ If the number of iterations is 0, this check fails; `loopi` requires at
+ least one iteration and will raise a LOOP error otherwise. The `loop`
+ instruction also has this requirement, but since the number of loop
+ iterations comes from a register it's harder to check statically and is not
+ considered here.
'''
out = CheckResult()
for loop in loops:
@@ -106,7 +105,7 @@
out = CheckResult()
for loop in loops:
for other in loops:
- if other.start in loop and not other.end in loop:
+ if other.start in loop and other.end not in loop:
out.err('Inner loop ends after outer loop (inner loop {}, '
'outer loop {})'.format(other, loop))
@@ -181,10 +180,13 @@
programmer must ensure that:
* Even if there are branches and jumps within a loop body, the final
- instruction of the loop body gets executed exactly once per iteration.
+ instruction of the loop body gets executed exactly once per
+ iteration.
+
* Nested loops have distinct end addresses.
- * The end instruction of an outer loop is not executed before an inner loop
- finishes.
+
+ * The end instruction of an outer loop is not executed before an inner
+ loop finishes.
In order to avoid simulating the control flow of the entire program to
check the first and third conditions, this check takes a conservative,
diff --git a/hw/ip/otbn/util/shared/check.py b/hw/ip/otbn/util/shared/check.py
index 315b8be..a99f0e5 100644
--- a/hw/ip/otbn/util/shared/check.py
+++ b/hw/ip/otbn/util/shared/check.py
@@ -14,7 +14,9 @@
out += first_check()
out += second_check()
out.warn('A warning')
- print(out.report()) # prints warnings/errors from both checks and "A warning"
+
+ # prints warnings/errors from both checks and "A warning"
+ print(out.report())
'''
def __init__(self):
self.errors = []
diff --git a/hw/ip/otbn/util/shared/decode.py b/hw/ip/otbn/util/shared/decode.py
index fc2b82a..6dac551 100644
--- a/hw/ip/otbn/util/shared/decode.py
+++ b/hw/ip/otbn/util/shared/decode.py
@@ -5,7 +5,7 @@
import struct
import sys
-from typing import Dict, Tuple
+from typing import Dict
from shared.elf import read_elf
from shared.insn_yaml import Insn, load_insns_yaml
