| commit | 48e810a074a816b6cc9488b5f1dadde5109d4c54 | [log] [tgz] |
|---|---|---|
| author | Prajwala Puttappa <prajwalaputtappa@lowrisc.org> | Thu Oct 28 17:03:25 2021 +0100 |
| committer | Rupert Swarbrick <rswarbrick@gmail.com> | Fri Nov 12 09:38:05 2021 +0000 |
| tree | 08c210d63ac42eb6c57bd97600a2959c5155c9cb | |
| parent | dd3a05bc5abc9dd2874896f171d12c6eaf1576f3 [diff] |
[otbn,dv] Changed dmem width to 32 bits from 256 bits Following methdos were modified: 1. load_u32: It reads 32 bit data and returns it. 2. load_u256: It reads 32 bits of data 8 times, packs it into 256 bits and returns it. 3. _commit_store: It unpacks 256 bits of data into eight 32 bits of data and writes it into the memory. Signed-off-by: Prajwala Puttappa <prajwalaputtappa@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
This repository contains hardware, software and utilities written as part of the OpenTitan project. It is structured as monolithic repository, or “monorepo”, where all components live in one repository. It exists to enable collaboration across partners participating in the OpenTitan project.
The project contains comprehensive documentation of all IPs and tools. You can access it online at docs.opentitan.org.
Have a look at CONTRIBUTING and our documentation on project organization and processes for guidelines on how to contribute code to this repository.
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).