tree: fce8a6d71e693a2db13d176eef613a476f4c9ff0 [path history] [tgz]
  1. bitstream/
  2. cdc/
  3. data/
  4. doc/
  5. dv/
  6. formal/
  7. ip/
  8. ip_templates/
  9. lint/
  10. rdc/
  11. syn/
  12. top_earlgrey/
  13. top_englishbreakfast/
  14. vendor/
  15. BUILD
  16. Makefile


This page serves as the landing spot for all hardware development within the OpenTitan project.

We start off by providing links to the results of various tool-flows run on all of our Comportable IPs. This includes DV simulations, FPV and lint, all of which are run with the dvsim tool which serves as the common frontend.

The Comportable IPs following it provides links to their design specifications and DV documents, and tracks their current stage of development. See the Hardware Development Stages for description of the hardware stages and how they are determined.

Next, we focus on all available processor cores and provide links to their design specifications, DV documents and the DV simulation results.

Finally, we provide the same set of information for all available top level designs.

Results of tool-flows

Comportable IPs

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Processor cores

Earl Grey chip-level results

Earl Grey-specific comportable IPs

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Hardware documentation overview

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