[pattgen/dv]updated pattgen with action items from v1 review
Signed-off-by: alex sapozhnikov <alex.sapozhnikov@wdc.com>
diff --git a/hw/ip/pattgen/data/pattgen_testplan.hjson b/hw/ip/pattgen/data/pattgen_testplan.hjson
index 8e2c24e..c6cd627 100644
--- a/hw/ip/pattgen/data/pattgen_testplan.hjson
+++ b/hw/ip/pattgen/data/pattgen_testplan.hjson
@@ -67,7 +67,7 @@
- Clear interrupts quickly
Checking:
- - Include functional cover point that rollover value is reached and counter is reset:
+ - Include functional cover point that rollover value is reached and counter is re-enabled:
- Ensure patterns are correctly generated
- Ensure interrupts are robust asserted and cleared (e.g. at the high data rate)
'''
@@ -75,37 +75,18 @@
tests: ["cnt_rollover"]
}
{
- name: alert
- desc: '''
- Checking alert errors
-
- Stimulus:
- TODO: identify exactly what alerts are triggered, and for the V2
- find out exactly what triggers alert, if anything
- Checking:
- - Check alert `fatal_fault_err` is triggered
- and err_code is `INVALID_CMD`
- - Check alert `recov_operation_err` is triggered
- and err_code is `INVALID_DATA`
- - Check that operations are not recoverable
- after `fatal_fault_err` alert
- '''
- milestone: V2
- tests: ["pattgen_alert"]
- }
- {
name: error
desc: '''
Reset then re-start the output channel on the fly.
Stimulus:
- Programm the configuration registers of the output channels
- - Randomly reset the in progress output channels
+ - Randomly re-enable the in progress output channels
- Re-program the configuration registers of the output channels
Checking:
- - Ensure patterns are dropped when reset
- - Ensure the output channels get back normal after reset
+ - Ensure patterns are dropped when re-enabled
+ - Ensure the output channels get back normal after re-enable
'''
milestone: V2
tests: ["pattgen_error"]
@@ -113,14 +94,8 @@
{
name: stress_all
desc: '''
- Combine above sequences in one test then randomly select for running.
-
- Stimulus:
- - Start sequences and randomly add reset between each sequence
-
- Checking:
- - All sequences should be finished and checked by the scoreboard
- '''
+ Stress_all test is a random mix of all the test above except csr tests.
+ '''
milestone: V2
tests: ["pattgen_stress_all"]
}
@@ -138,9 +113,6 @@
* One bit width variables are wrapped in one cover point
while counters and data have designated cover points
* Channel enable signal is stand alone cover point
- * Chennel enable signal is crossed with all other cover points
- * When both channels are active, the enable signals of each
- channel are each crossed with cover points of both channels
'''
}
{
@@ -170,27 +142,10 @@
'''
}
{
- name: alert_cg
- desc: '''
- Covers fatal fault error alert when forcing command error
- and recover operation error alert when forcing data error.
- Individual alert settings and signals that will be covered include:
- - fatal fault error alert
- - recoverable operation error alert
- '''
- }
- {
name: inter_cg
desc: '''
- Covers that all valid settings of Interrupt Enable Register
- and Interrupt State Register register have been tested.
- Individual interrupt settings that will be covered include:
- - Interrupt Enable Register[0] (done_ch0)
- - Interrupt Enable Register[1] (done_ch1)
- - Interrupt State Register[0] (done_ch0)
- - Interrupt State Register[1] (done_ch1)
- Combinations of Interrupt Enable and Interrupt State
- registers for each channel will be crossed
+ intr_cg is defined in cip_base_env_cov and
+ referenced in pattgen_scoreboard
'''
}
{
@@ -245,7 +200,8 @@
Covers various data_0 values of the channel0 seed pattern ranges,
to ensure that Pattgen can operate successfully on different pattern lengths.
we will cover that an acceptable distribution of lengths has been seen,
- and specifically cover corner cases.
+ and specifically cover corner cases. The covergroup takes data from
+ TL_UL scoreboard input
'''
}
{
@@ -266,6 +222,12 @@
Similar to pattern_data_ch0_1_cg.
'''
}
+ {
+ name: program_while_busy_cg
+ desc: '''
+ Program the DUT while pattern is being produced to insure current pattern is not being corrupt.
+ '''
+ }
]
diff --git a/hw/ip/pattgen/doc/checklist.md b/hw/ip/pattgen/doc/checklist.md
index 38d5546..a47996f 100644
--- a/hw/ip/pattgen/doc/checklist.md
+++ b/hw/ip/pattgen/doc/checklist.md
@@ -118,7 +118,7 @@
Type | Item | Resolution | Note/Collaterals
--------------|---------------------------------------|-------------|------------------
-Documentation | [DV_DOC_DRAFT_COMPLETED][] | Not Started | [Pattgen DV document]({{<relref "dv" >}})
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [Pattgen DV document]({{<relref "dv" >}})
Documentation | [TESTPLAN_COMPLETED][] | Done | [Pattgen Testplan]({{<relref "dv/index.md#testplan" >}})
Testbench | [TB_TOP_CREATED][] | Done |
Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done |
@@ -137,7 +137,7 @@
Code Quality | [TB_LINT_SETUP][] | Done |
Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | N/A | Except for IP module
Review | [DESIGN_SPEC_REVIEWED][] | Done |
-Review | [TESTPLAN_REVIEWED][] | Not Started |
+Review | [TESTPLAN_REVIEWED][] | Done |
Review | [STD_TEST_CATEGORIES_PLANNED][] | Done | Exception (Security, Power, Debug)
Review | [V2_CHECKLIST_SCOPED][] | Done |
