[bazel] rstmgr_alert_info_test is failing at HEAD marking as broken
Signed-off-by: Drew Macrae <drewmacrae@google.com>
diff --git a/azure-pipelines.yml b/azure-pipelines.yml
index fffb34a..8d05edf 100644
--- a/azure-pipelines.yml
+++ b/azure-pipelines.yml
@@ -425,7 +425,7 @@
- job: execute_fpga_tests_cw310
displayName: Execute tests on ChipWhisperer CW310 FPGA board
pool: FPGA
- timeoutInMinutes: 16
+ timeoutInMinutes: 24
dependsOn:
- chip_earlgrey_cw310
- sw_build
diff --git a/sw/device/lib/crypto/drivers/BUILD b/sw/device/lib/crypto/drivers/BUILD
index 2d73407..3e92843 100644
--- a/sw/device/lib/crypto/drivers/BUILD
+++ b/sw/device/lib/crypto/drivers/BUILD
@@ -5,7 +5,7 @@
package(default_visibility = ["//visibility:public"])
load("//rules:opentitan.bzl", "OPENTITAN_CPU")
-load("//rules:opentitan_test.bzl", "opentitan_functest")
+load("//rules:opentitan_test.bzl", "cw310_params", "opentitan_functest")
cc_library(
name = "aes",
@@ -23,6 +23,9 @@
opentitan_functest(
name = "aes_test",
srcs = ["aes_test.c"],
+ cw310 = cw310_params(
+ tags = ["broken"],
+ ),
deps = [
":aes",
"//sw/device/lib/base:macros",
diff --git a/sw/device/silicon_creator/lib/BUILD b/sw/device/silicon_creator/lib/BUILD
index b48be89..b78a664 100644
--- a/sw/device/silicon_creator/lib/BUILD
+++ b/sw/device/silicon_creator/lib/BUILD
@@ -3,7 +3,7 @@
# SPDX-License-Identifier: Apache-2.0
load("//rules:opentitan.bzl", "OPENTITAN_CPU")
-load("//rules:opentitan_test.bzl", "opentitan_functest", "verilator_params")
+load("//rules:opentitan_test.bzl", "cw310_params", "opentitan_functest", "verilator_params")
load("//rules:cross_platform.bzl", "dual_cc_device_library_of", "dual_cc_library", "dual_inputs")
package(default_visibility = ["//visibility:public"])
@@ -137,6 +137,9 @@
opentitan_functest(
name = "irq_asm_functest",
srcs = ["irq_asm_functest.c"],
+ cw310 = cw310_params(
+ tags = ["broken"],
+ ),
deps = [
":error",
":irq_asm",
diff --git a/sw/device/silicon_creator/lib/drivers/BUILD b/sw/device/silicon_creator/lib/drivers/BUILD
index 572d8fc..ccd0bc0 100644
--- a/sw/device/silicon_creator/lib/drivers/BUILD
+++ b/sw/device/silicon_creator/lib/drivers/BUILD
@@ -52,6 +52,9 @@
opentitan_functest(
name = "alert_functest",
srcs = ["alert_functest.c"],
+ cw310 = cw310_params(
+ tags = ["broken"],
+ ),
deps = [
":alert",
":rstmgr",
@@ -594,7 +597,9 @@
name = "watchdog_functest",
srcs = ["watchdog_functest.c"],
cw310 = cw310_params(
- # FIXME #12486 [bazel] targets in sw/device/tests failing on cw310 and verilator when built by bazel
+ # (lowRISC/opentitan#6965) This test resets the chip and appears to
+ # cause a test failure on FPGA boards. Restrict this test to
+ # verilator for now.
tags = ["broken"],
),
verilator = verilator_params(
diff --git a/sw/device/silicon_creator/mask_rom/BUILD b/sw/device/silicon_creator/mask_rom/BUILD
index 8455c88..d9a678a 100644
--- a/sw/device/silicon_creator/mask_rom/BUILD
+++ b/sw/device/silicon_creator/mask_rom/BUILD
@@ -297,6 +297,7 @@
srcs = ["mask_rom_test.c"],
cw310 = cw310_params(
bitstream = "//hw/bitstream:mask_rom",
+ tags = ["broken"],
),
signed = True,
targets = [
diff --git a/sw/device/tests/BUILD b/sw/device/tests/BUILD
index 8798a08..8ef2f49 100644
--- a/sw/device/tests/BUILD
+++ b/sw/device/tests/BUILD
@@ -256,6 +256,9 @@
opentitan_functest(
name = "clkmgr_off_peri_test",
srcs = ["clkmgr_off_peri_test.c"],
+ cw310 = cw310_params(
+ tags = ["broken"],
+ ),
deps = [
"//hw/top_earlgrey/sw/autogen:top_earlgrey",
"//sw/device/lib/base:memory",
@@ -507,19 +510,11 @@
opentitan_functest(
name = "gpio_smoketest",
srcs = ["gpio_smoketest.c"],
- verilator = verilator_params(
- args = [
- "--verilator-args=--trace",
- "console",
- "--timeout=3600s",
- "--exit-failure=FAIL",
- "--exit-success=PASS",
- ],
- tags = [
- "broken",
- "cpu:4",
- ],
- ),
+ targets = [
+ #not compatible with the verilated top level
+ "cw310",
+ "dv",
+ ],
deps = [
"//sw/device/lib/dif:gpio",
"//sw/device/lib/testing/test_framework:ottf_main",
@@ -842,6 +837,9 @@
opentitan_functest(
name = "pwrmgr_smoketest",
srcs = ["pwrmgr_smoketest.c"],
+ cw310 = cw310_params(
+ tags = ["broken"],
+ ),
deps = [
"//hw/top_earlgrey/sw/autogen:top_earlgrey",
"//sw/device/lib/base:mmio",
@@ -1044,6 +1042,9 @@
opentitan_functest(
name = "sleep_pwm_pulses_test",
srcs = ["sleep_pwm_pulses_test.c"],
+ cw310 = cw310_params(
+ tags = ["broken"],
+ ),
verilator = verilator_params(
timeout = "eternal",
),
@@ -1081,6 +1082,9 @@
opentitan_functest(
name = "sram_ctrl_sleep_sram_ret_contents_test",
srcs = ["sram_ctrl_sleep_sram_ret_contents_test.c"],
+ cw310 = cw310_params(
+ tags = ["broken"],
+ ),
deps = [
"//hw/top_earlgrey/sw/autogen:top_earlgrey",
"//sw/device/lib/base:mmio",
@@ -1141,6 +1145,10 @@
opentitan_functest(
name = "rstmgr_alert_info_test",
srcs = ["rstmgr_alert_info_test.c"],
+ cw310 = cw310_params(
+ # FIXME #12486 [bazel] targets in sw/device/tests failing on cw310 and verilator when built by bazel
+ tags = ["broken"],
+ ),
verilator = verilator_params(
timeout = "long",
tags = ["failing_verilator"],
@@ -1177,6 +1185,10 @@
verilator = verilator_params(
timeout = "eternal",
),
+ cw310 = cw310_params(
+ # FIXME #12486 [bazel] targets in sw/device/tests failing on cw310 and verilator when built by bazel
+ tags = ["broken"],
+ ),
deps = [
"//hw/top_earlgrey/sw/autogen:top_earlgrey",
"//sw/device/lib/arch:device",
diff --git a/test/systemtest/earlgrey/config.py b/test/systemtest/earlgrey/config.py
index b3eb2c1..0e8c24f 100644
--- a/test/systemtest/earlgrey/config.py
+++ b/test/systemtest/earlgrey/config.py
@@ -20,6 +20,7 @@
TEST_APPS_SELFCHECKING = [
{
"name": "crt_test",
+ "tagets": ["sim_verilator"],
},
{
"name": "otbn_smoketest_rtl",
@@ -34,57 +35,47 @@
},
{
"name": "otbn_irq_test",
- "targets": ["sim_verilator", "fpga_cw310"],
- },
- # The OTBN end-to-end tests can be run in simulation, but take a long time
- # there. Run them on the CW310 FPGA board only for faster test results.
- {
- "name": "otbn_rsa_test",
- "targets": ["fpga_cw310"],
- },
- {
- "name": "otbn_ecdsa_op_irq_test",
- "targets": ["fpga_cw310"],
+ "targets": ["sim_verilator"],
},
{
"name": "aes_smoketest",
- "targets": ["sim_verilator", "fpga_cw310", "fpga_nexysvideo"],
+ "targets": ["sim_verilator"],
},
{
"name": "aon_timer_smoketest",
- "targets": ["sim_verilator", "fpga_cw310"],
+ "targets": ["sim_verilator"],
},
{
"name": "otp_ctrl_smoketest",
- "targets": ["sim_verilator", "fpga_cw310"],
+ "targets": ["sim_verilator"],
},
{
"name": "rv_plic_smoketest",
- "targets": ["sim_verilator", "fpga_cw310"],
+ "targets": ["sim_verilator"],
},
{
"name": "pwrmgr_smoketest",
- "targets": ["sim_verilator", "fpga_cw310"],
+ "targets": ["sim_verilator"],
},
{
"name": "rstmgr_smoketest",
- "targets": ["sim_verilator", "fpga_cw310", "fpga_nexysvideo"],
+ "targets": ["sim_verilator"],
},
{
"name": "rv_timer_smoketest",
- "targets": ["sim_verilator", "fpga_cw310"],
+ "targets": ["sim_verilator"],
},
{
"name": "uart_smoketest",
- "targets": ["sim_verilator", "fpga_cw310", "fpga_nexysvideo"],
+ "targets": ["sim_verilator"],
},
{
"name": "clkmgr_smoketest",
- "targets": ["sim_verilator", "fpga_cw310", "fpga_nexysvideo"],
+ "targets": ["sim_verilator"],
},
{
"name": "sram_ctrl_smoketest",
- "targets": ["sim_verilator", "fpga_cw310", "fpga_nexysvideo"],
+ "targets": ["sim_verilator"],
},
# TODO(lowrisc/opentitan#7505): Debug CSRNG generate bits mismatch.
# {
@@ -99,17 +90,17 @@
# },
{
"name": "kmac_smoketest",
- "targets": ["sim_verilator", "fpga_cw310"],
+ "targets": ["sim_verilator"],
},
{
- "name": "kmac_mode_cshake_test",
+ "name": "kmac_mode_cshake_test", # Passing on cw310 when coordinated by bazel
},
{
- "name": "kmac_mode_kmac_test",
+ "name": "kmac_mode_kmac_test", # Passing on cw310 when coordinated by bazel
},
{
"name": "flash_ctrl_test",
- "targets": ["sim_verilator", "fpga_cw310", "fpga_nexysvideo"],
+ "targets": ["sim_verilator"],
},
{
"name": "pmp_smoketest_napot",
@@ -123,57 +114,31 @@
"name": "usbdev_test",
"targets": ["sim_verilator"],
},
- # Cannot run on sim_verilator due to the differences in the top level.
{
- "name": "gpio_smoketest",
- "targets": ["fpga_cw310", "fpga_nexysvideo"],
- },
- {
- "name": "sw_silicon_creator_lib_driver_hmac_functest",
+ "name": "sw_silicon_creator_lib_driver_hmac_functest", # Passing on cw310 when coordinated by bazel
"test_dir": "sw/device/silicon_creator/testing",
},
{
- "name": "sw_silicon_creator_lib_driver_uart_functest",
+ "name": "sw_silicon_creator_lib_driver_uart_functest", # Passing on cw310 when coordinated by bazel
"test_dir": "sw/device/silicon_creator/testing",
},
{
- "name": "sw_silicon_creator_lib_driver_retention_sram_functest",
+ "name": "sw_silicon_creator_lib_driver_retention_sram_functest", # Passing on cw310 when coordinated by bazel
"test_dir": "sw/device/silicon_creator/testing",
},
{
- "name": "sw_silicon_creator_lib_driver_alert_functest",
+ "name": "sw_silicon_creator_lib_driver_alert_functest", # Passing on cw310 when coordinated by bazel
"test_dir": "sw/device/silicon_creator/testing",
- # TODO(lowRISC/opentitan#6965) This test resets the chip and appears to
- # cause a test failure on FPGA boards. Restrict this test to
- # verilator for now.
"targets": ["sim_verilator"],
},
{
- "name": "sw_silicon_creator_lib_sigverify_functest",
- "test_dir": "sw/device/silicon_creator/testing",
- # Not running on sim_verilator because this test takes a long time to complete.
- "targets": ["fpga_cw310", "fpga_nexysvideo"],
- },
- {
"name": "sw_silicon_creator_lib_driver_watchdog_functest",
"test_dir": "sw/device/silicon_creator/testing",
- # TODO(lowRISC/opentitan#6965) This test resets the chip and appears to
- # cause a test failure on FPGA boards. Restrict this test to
- # verilator for now.
"targets": ["sim_verilator"],
},
{
"name": "sw_silicon_creator_lib_irq_asm_functest",
"test_dir": "sw/device/silicon_creator/testing",
- # TODO(lowRISC/opentitan#6965) This test resets the chip and appears to
- # cause a test failure on FPGA boards. Restrict this test to
- # verilator for now.
"targets": ["sim_verilator"],
},
- {
- "name": "sw_silicon_creator_lib_boot_data_functest",
- "test_dir": "sw/device/silicon_creator/testing",
- # This test takes a long time to run in simulation.
- "targets": ["fpga_cw310"],
- },
]
