| commit | 47bb433aad2bce2f8511a20caeb9fe02aa89abb1 | [log] [tgz] |
|---|---|---|
| author | Canberk Topal <ctopal@lowrisc.org> | Mon Aug 02 14:21:13 2021 +0100 |
| committer | Greg Chadwick <mail@gregchadwick.co.uk> | Tue Aug 03 11:01:01 2021 +0100 |
| tree | 0c667150bf61de05f15ee112c3e05d89b45b26ec | |
| parent | f94a3c7d56a4e4f0374c0de8ab5ec94375f9ad28 [diff] |
[rtl] Bug Fix related to SRLI/SLLI Decoding This commit fixes a bug where the SRLI or SLLI instruction passes as valid when they have 25/26 bitfields as 1. In ISA they would not have 1 at their 25/26th bitfields. Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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