[entropy_src/rtl] Provide backpressure on core FIFOs

The DV changes added in PR #14643 immediately revealed that there are
some gaps in the backpressure pipeline in the entropy_src core, and
that stalls from the cs_aes_halt_ack can cause entropy to be dropped
before it gets SHA conditioner, which could lead to poor entropy
outputs if enough entropy is dropped.

This PR corrects the problem by applying consistent backpressure
throughout the entropy_src data processing chain.  With a
long enough delay entropy can be stalled all the way back at the
RNG input. Even if the external RNG source does not support
backpressure, this is fine because entropy dropped at the is not
counted when calculating the number of inputs gathered to create
the output seeds.

Applying backpressure all the way back to the RNG input also helps
for verification, as the test environement does support backpressure
at this interface.

-----

This commit also manipulates the timing of the internal enable
signals, as the new backpressure changes introduce one timing wrinkle.
Since RNG bit-select mode introduces an additional packer fifo stage
this creates a one cycle delay that comes and goes whether the RNG
bit select fifo is enabled, which can cause dropped samples at
disable time, and these particular samples are difficult to handle in
verification.  Therefore the enable/disable signal for most of the core
is delayed by one additional clock cycle.

This delayed enable signal is only used by processing stages after the
RNG bit select FIFO (which is most of the core).  Inputs to the
bit-select and RNG input FIFOs use separate enable signals.

Signed-off-by: Martin Lueker-Boden <martin.lueker-boden@wdc.com>
Co-authored-by: Mark Branstad <mark.branstad@wdc.com>
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README.md

OpenTitan

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