[csrng/dv] Updated testplan, Added cfg cover group
Signed-off-by: Steve Nelson <steve.nelson@wdc.com>
diff --git a/hw/ip/csrng/data/csrng_testplan.hjson b/hw/ip/csrng/data/csrng_testplan.hjson
index 4ca7a8d..2913075 100644
--- a/hw/ip/csrng/data/csrng_testplan.hjson
+++ b/hw/ip/csrng/data/csrng_testplan.hjson
@@ -12,22 +12,13 @@
{
name: smoke
desc: '''
- Enable csrng, send instantiate/generate cmds, verify genbits/interrupt.
+ Verify sending instantiate/generate cmds via SW path.
+ Verify reading genbits via SW path.
'''
milestone: V1
tests: ["csrng_smoke"]
}
{
- name: firmware
- desc: '''
- Verify ability to access genbits register based on value of efuse input.
- Verify regen bit disables write access of control registers.
- Verify registers at End-Of-Test.
- '''
- milestone: V2
- tests: []
- }
- {
name: interrupts
desc: '''
Verify cs_cmd_req_done interrupt asserts/clears as predicted.
@@ -47,6 +38,10 @@
Verify above for all valid values of acmd, clen, flags, glen.
Verify for multiple hw app interfaces running in parallel.
Verify sw/hw app interfaces running in parallel.
+ Verify internal state for sw/hw apps.
+ Verify genbits generated as predicted.
+ Verify fips bit is passed through properly.
+ Verify ability to access registers based on otp, enables.
'''
milestone: V2
tests: ["csrng_cmds"]
@@ -55,17 +50,6 @@
name: life cycle
desc: '''
Verify lifecycle hardware debug mode enables AES bypass, reading CSRNG internal state.
- Verify CSRNG internal state for all csrng/genbits operations.
- '''
- milestone: V2
- tests: []
- }
- {
- name: genbits
- desc: '''
- Verify genbits generated as predicted.
- Verify fips bits is passed through properly.
- Verify for multiple hw app interfaces running in parallel.
'''
milestone: V2
tests: []
diff --git a/hw/ip/csrng/dv/cov/csrng_cov_if.sv b/hw/ip/csrng/dv/cov/csrng_cov_if.sv
index 0cdf9e9..bca0be1 100644
--- a/hw/ip/csrng/dv/cov/csrng_cov_if.sv
+++ b/hw/ip/csrng/dv/cov/csrng_cov_if.sv
@@ -3,6 +3,7 @@
// SPDX-License-Identifier: Apache-2.0
//
// Implements functional coverage for csrng.
+
interface csrng_cov_if (
input logic clk_i
);
@@ -12,6 +13,7 @@
import csrng_pkg::*;
import csrng_agent_pkg::*;
import csrng_env_pkg::*;
+ import prim_mubi_pkg::*;
`include "dv_fcov_macros.svh"
bit en_full_cov = 1'b1;
@@ -21,8 +23,22 @@
bit en_intg_cov_loc;
assign en_intg_cov_loc = en_full_cov | en_intg_cov;
+ covergroup csrng_cfg_cg with function sample(mubi8_t otp_en_cs_sw_app_read,
+ mubi4_t sw_app_enable,
+ mubi4_t read_int_state
+ );
+ option.name = "csrng_cfg_cg";
+ option.per_instance = 1;
+
+ cp_otp_en_cs_sw_app_read: coverpoint otp_en_cs_sw_app_read;
+
+ cp_sw_app_enable: coverpoint sw_app_enable;
+
+ cp_read_int_state: coverpoint read_int_state;
+ endgroup : csrng_cfg_cg
+
covergroup csrng_cmds_cg with function sample(bit[NUM_HW_APPS-1:0] hwapp,
- csrng_pkg::acmd_e acmd,
+ acmd_e acmd,
bit[3:0] clen,
bit[3:0] flags,
bit[18:0] glen
@@ -37,9 +53,9 @@
}
cp_clen: coverpoint clen {
- bins zero = { 0 };
- bins additional_data = { [1:12] };
- bins invalid = { [13:15] };
+ bins no_additional_data = { 0 };
+ bins additional_data = { [1:12] };
+ bins invalid = { [13:15] };
}
cp_flags: coverpoint flags {
@@ -59,10 +75,18 @@
cr_acmd_glen: cross cp_acmd, cp_glen;
endgroup : csrng_cmds_cg
+ `DV_FCOV_INSTANTIATE_CG(csrng_cfg_cg, en_full_cov)
`DV_FCOV_INSTANTIATE_CG(csrng_cmds_cg, en_full_cov)
// Sample functions needed for xcelium
- function automatic void cg_cmds_sample(bit[NUM_HW_APPS-1:0] hwapp, csrng_item cs_item);
+ function automatic void cg_cfg_sample(csrng_env_cfg cfg);
+ csrng_cfg_cg_inst.sample(cfg.otp_en_cs_sw_app_read,
+ cfg.sw_app_enable,
+ cfg.read_int_state
+ );
+ endfunction
+
+ function automatic void cg_cmds_sample(bit[NUM_HW_APPS-1:0] hwapp, csrng_item cs_item);
csrng_cmds_cg_inst.sample(hwapp,
cs_item.acmd,
cs_item.clen,
diff --git a/hw/ip/csrng/dv/env/seq_lib/csrng_base_vseq.sv b/hw/ip/csrng/dv/env/seq_lib/csrng_base_vseq.sv
index 5648a5e..f8cde7f 100644
--- a/hw/ip/csrng/dv/env/seq_lib/csrng_base_vseq.sv
+++ b/hw/ip/csrng/dv/env/seq_lib/csrng_base_vseq.sv
@@ -11,12 +11,23 @@
`uvm_object_utils(csrng_base_vseq)
`uvm_object_new
- bit do_csrng_init = 1'b1;
- bit [TL_DW-1:0] rdata;
+ bit do_csrng_init = 1'b1;
+ bit [TL_DW-1:0] rdata;
+
+ virtual csrng_cov_if cov_vif;
+
push_pull_device_seq#(entropy_src_pkg::FIPS_CSRNG_BUS_WIDTH) m_entropy_src_pull_seq;
push_pull_host_seq#(csrng_pkg::CSRNG_CMD_WIDTH) m_edn_push_seq[NUM_HW_APPS];
+ virtual task body();
+ if (!uvm_config_db#(virtual csrng_cov_if)::get(null, "*.env" , "csrng_cov_if", cov_vif)) begin
+ `uvm_fatal(`gfn, $sformatf("Failed to get csrng_cov_if from uvm_config_db"))
+ end
+
+ cov_vif.cg_cfg_sample(.cfg(cfg));
+ endtask
+
virtual task dut_init(string reset_kind = "HARD");
super.dut_init(reset_kind);
if (do_csrng_init) csrng_init();
diff --git a/hw/ip/csrng/dv/env/seq_lib/csrng_cmds_vseq.sv b/hw/ip/csrng/dv/env/seq_lib/csrng_cmds_vseq.sv
index 633a8ba..354c703 100644
--- a/hw/ip/csrng/dv/env/seq_lib/csrng_cmds_vseq.sv
+++ b/hw/ip/csrng/dv/env/seq_lib/csrng_cmds_vseq.sv
@@ -65,6 +65,8 @@
endfunction
task body();
+ super.body();
+
// Create entropy_src sequence
m_entropy_src_pull_seq = push_pull_device_seq#(entropy_src_pkg::FIPS_CSRNG_BUS_WIDTH)::
type_id::create("m_entropy_src_pull_seq");
diff --git a/hw/ip/csrng/dv/env/seq_lib/csrng_smoke_vseq.sv b/hw/ip/csrng/dv/env/seq_lib/csrng_smoke_vseq.sv
index c0afffa..6a8b522 100644
--- a/hw/ip/csrng/dv/env/seq_lib/csrng_smoke_vseq.sv
+++ b/hw/ip/csrng/dv/env/seq_lib/csrng_smoke_vseq.sv
@@ -10,6 +10,8 @@
csrng_item cs_item;
task body();
+ super.body();
+
cs_item = csrng_item::type_id::create("cs_item");
// Create/Write CSRNG Cmd_Req - Instantiate Command
