commit 46ede4b6618283bf3b449d7cdfa09087f640ed0b
author Greg Chadwick <gac@lowrisc.org> Tue Jan 14 12:46:39 2020 +0000
committer Pirmin Vogel <vogelpi@lowrisc.org> Thu Feb 06 10:13:38 2020 +0100
tree 343440112f2c7268cd71b1bb110724b4493333eb
parent cf4230893d7b2369dc6b3d8c1bb154bba9febcbf

[hw] Add default clk/rst for prim_assert macros

Fixes #1259

Signed-off-by: Greg Chadwick <gac@lowrisc.org>

util/reggen/reg_top.sv.tpl

diff --git a/util/reggen/reg_top.sv.tpl b/util/reggen/reg_top.sv.tpl
index 08f9ad7..bb689db 100644
--- a/util/reggen/reg_top.sv.tpl
+++ b/util/reggen/reg_top.sv.tpl
@@ -369,16 +369,16 @@
   end
 
   // Assertions for Register Interface
-  `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
-  `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)
+  `ASSERT_PULSE(wePulse, reg_we)
+  `ASSERT_PULSE(rePulse, reg_re)
 
-  `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid, clk_i, !rst_ni)
+  `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid)
 
-  `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)
+  `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit))
 
   // this is formulated as an assumption such that the FPV testbenches do disprove this
   // property by mistake
-  `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0, clk_i, !rst_ni)
+  `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0)
 
 endmodule
 <%def name="str_bits_sv(msb, lsb)">\