| commit | 46e11ba66e9c70ca08afd56ef829f2e7f535c053 | [log] [tgz] |
|---|---|---|
| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Tue Jul 13 12:11:43 2021 +0100 |
| committer | Rupert Swarbrick <rswarbrick@gmail.com> | Sat Jul 17 14:57:54 2021 +0100 |
| tree | e7b0797e4662ef71fb9338f99f6b5c28b6e3eb78 | |
| parent | e3e7610e2c87746c25b3c32dc968b7f4e1de2c37 [diff] |
[otbn] Fix BN.LID when the destination WDR is read from x1
The problem comes up with an instruction like:
bn.lid x1, 0(x0)
The previous code read both input GPRs to BN.LID (x1 and x0) on the
first cycle. This is good for the base address, but is the wrong thing
for the destination address, which is needed on the following cycle.
Note that the behaviour was technically wrong for something like
bn.lid x2, 0(x0)
as well, but didn't cause a bug because the base register file doesn't
factor the read-enable in unless we're reading from the call stack.
To see the bug, run the following example code:
addi x1, x0, 1
bn.lid x1, 0(x0)
ecall
.section .data
.word 0x00000000
.word 0x00000001
.word 0x00000002
.word 0x00000003
.word 0x00000004
.word 0x00000005
.word 0x00000006
.word 0x00000007
If that is saved as bug.s, assemble and link it with
hw/ip/otbn/util/otbn-as -o bug.o bug.s
hw/ip/otbn/util/otbn-ld -o bug bug.o
Next, build a Verilator-based simulation with:
fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ip:otbn_top_sim
and then run it with:
build/lowrisc_ip_otbn_top_sim_0.1/sim-verilator/Votbn_top_sim -t --load-elf=bug
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
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