| commit | 41fd2b0005e98d40674e4ea4fb1daf482b0bb847 | [log] [tgz] |
|---|---|---|
| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Thu Dec 03 12:16:39 2020 +0000 |
| committer | Sam Elliott <sam@lenary.co.uk> | Thu Dec 03 17:14:36 2020 +0000 |
| tree | d71d1ffae18cb6632a1d3f0bf0fbed8c39685939 | |
| parent | 4b41116e388e448bb06a3471ef0c4aa07e1ab58b [diff] |
[otbn] Remove "err" interrupt We're going to consolidate these interrupts, so the only one is the "done" interrupt. To spot errors, the host software can use the ERR_CODE status register. This patch looks big because of auto-generated code, but the only manual changes to hardware are: - otbn.hjson: Remove the interrupt - otbn.sv: Remove the interrupt and tidy up the error code logic - tb.sv: Remove a top-level connection The manual changes to software are also small: although we've now just got one interrupt type, the DIF style is to keep an explicit index, so all we really do is remove an entry from the enum. There's also a manually entered count of interrupts in dif_plic.c which needs updating. In software test code, we remove various entries from dif_otbn_unittest.cc. The interrupt tests try the first and last interrupts, which doesn't make sense when there's just one, so this patch removes the "last" part each time. Finally, we have to change an interrupt count in dif_plic_unittest.cc. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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