[spi_host/dv]Modified Pass Through Test and Review Changes
- Modified Error Cmd Test
- Modified Passthrough Test
- Added Structs To DV Doc
- Changed Winbond to V3 In TestPlan
- CG Updated in TestPlan
- Modified Event And Stress Seq as per Review
- Modified Event And Error As Per Review
- Modified Event With Check Error and Event tasks
- Modifications As Per Review
- Renamed Error TX RX Test To Overflow Underflow
- Removed sck_gate_en From Tb
- Passthrough Os Clarified To Pull High
Signed-off-by: Viswanadha Bazawada <viswanadha.bazawada@ensilica.com>
diff --git a/hw/ip/spi_host/data/spi_host_testplan.hjson b/hw/ip/spi_host/data/spi_host_testplan.hjson
index dedb77f..39b252d 100644
--- a/hw/ip/spi_host/data/spi_host_testplan.hjson
+++ b/hw/ip/spi_host/data/spi_host_testplan.hjson
@@ -61,7 +61,7 @@
once the event interrupt pin is asserted
'''
milestone: V2
- tests: ["spi_host_error_txrx", "spi_host_error_cmd", "spi_host_event"]
+ tests: ["spi_host_overflow_underflow", "spi_host_error_cmd", "spi_host_event"]
}
{
name: clock_rate
@@ -126,9 +126,9 @@
- Verify the function of spi_host in passthrough_mode
Stimulus:
- - TBD
+ - Enable Passthrough Mode
Checking:
- - TBD
+ - Ensure Host to Device and Device to Host paths are switched to Passthrough ports
'''
milestone: V2
tests: ["spi_host_passthrough_mode"]
@@ -158,19 +158,6 @@
tests: []
}
{
- name: endian
- desc: '''
- Stimulus:
- - set the compile time parameter to configure the DUT in both modes.
- if possible this should be randomized for all test to verify support in both modes
-
- Checking:
- - Check all features are supported correctly in both little and big endian mode
- '''
- milestone: V2
- tests: []
- }
- {
name: duplex
desc: '''
Stimulus:
@@ -225,7 +212,7 @@
- Verify the DUT against the WindBond bfm by making the spi agent passive
to verify that we comply with the spi targeted for opentitan
'''
- milestone: V2
+ milestone: V3
tests: []
}
]
@@ -288,12 +275,6 @@
'''
}
{
- name: alert_cg
- desc: '''
- Collect coverage to verify all alerts are triggered correctly
- '''
- }
- {
name: control_cg
desc: '''
Collect coverage on the control register to make sure all options are excercised
diff --git a/hw/ip/spi_host/doc/dv/index.md b/hw/ip/spi_host/doc/dv/index.md
index d02df31..8839522 100644
--- a/hw/ip/spi_host/doc/dv/index.md
+++ b/hw/ip/spi_host/doc/dv/index.md
@@ -126,6 +126,47 @@
bit [15:8] rx_qd;
bit [7:0] tx_qd;
} spi_host_status_t;
+
+ typedef struct packed{
+ bit csidinval;
+ bit cmdinval;
+ bit underflow;
+ bit overflow;
+ bit cmdbusy;
+ } spi_host_error_enable_t;
+
+ typedef struct packed{
+ bit accessinval;
+ bit csidinval;
+ bit cmdinval;
+ bit underflow;
+ bit overflow;
+ bit cmdbusy;
+ } spi_host_error_status_t;
+
+ typedef struct packed{
+ bit idle;
+ bit ready;
+ bit txwm;
+ bit rxwm;
+ bit txempty;
+ bit rxfull;
+ } spi_host_event_enable_t;
+
+ typedef struct{
+ bit spi_event;
+ bit error;
+ } spi_host_intr_state_t;
+
+ typedef struct{
+ bit spi_event;
+ bit error;
+ } spi_host_intr_enable_t;
+
+ typedef struct{
+ bit spi_event;
+ bit error;
+ } spi_host_intr_test_t;
```
### TL_agent
@@ -170,7 +211,7 @@
* generate_transaction()
Generates a SPI transaction of n segments with command, address, dummy and data segements
-
+
* read_rx_fifo()
Read available data in the RX fifo
diff --git a/hw/ip/spi_host/dv/env/seq_lib/spi_host_base_vseq.sv b/hw/ip/spi_host/dv/env/seq_lib/spi_host_base_vseq.sv
index a9a37e6..d72b9a4 100644
--- a/hw/ip/spi_host/dv/env/seq_lib/spi_host_base_vseq.sv
+++ b/hw/ip/spi_host/dv/env/seq_lib/spi_host_base_vseq.sv
@@ -157,6 +157,10 @@
virtual task program_spi_host_regs();
// IMPORTANT: configopt regs must be programmed before command reg
+ `DV_CHECK_RANDOMIZE_FATAL(ral.error_enable)
+ csr_update(.csr(ral.error_enable));
+ `DV_CHECK_RANDOMIZE_FATAL(ral.event_enable)
+ csr_update(.csr(ral.event_enable));
`DV_CHECK_RANDOMIZE_FATAL(ral.intr_enable)
csr_update(.csr(ral.intr_enable));
program_configopt_regs();
diff --git a/hw/ip/spi_host/dv/env/seq_lib/spi_host_error_cmd_vseq.sv b/hw/ip/spi_host/dv/env/seq_lib/spi_host_error_cmd_vseq.sv
new file mode 100644
index 0000000..0b0e1ff
--- /dev/null
+++ b/hw/ip/spi_host/dv/env/seq_lib/spi_host_error_cmd_vseq.sv
@@ -0,0 +1,49 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// error_cmd test vseq
+// test tries to capture error interrupt when cmd invalid condition appears
+// cmd invalid is created when cmd sent and host isnt ready
+class spi_host_error_cmd_vseq extends spi_host_tx_rx_vseq;
+ `uvm_object_utils(spi_host_error_cmd_vseq)
+ `uvm_object_new
+
+ spi_segment_item segment;
+
+ virtual task body();
+ bit [7:0] read_q[$];
+ bit [7:0] txqd;
+ spi_host_intr_state_t intr_state;
+ int num_transactions = 6;
+ int cmdq_depth = 5;
+ bit cmd_not_ready = 1'b0;
+
+ program_spi_host_regs();
+ cfg.seq_cfg.host_spi_min_len = 4;
+ cfg.seq_cfg.host_spi_max_len = 16;
+ for (int i = 0; i < (cmdq_depth + 2); i++) begin
+ generate_transaction();
+ segment = new();
+ if(i < (cmdq_depth + 1)) begin
+ check_error(ral.error_status.cmdbusy, 0);
+ end else begin
+ check_error(ral.error_status.cmdbusy, 1);
+ end
+ while (transaction.segments.size() > 0) begin
+ segment = transaction.segments.pop_back();
+ if (segment.command_reg.direction != RxOnly) begin
+ access_data_fifo(segment.spi_data, TxFifo,1'b0);
+ end
+ end
+ program_command_reg(segment.command_reg);
+ end // endfor
+
+ endtask : body
+
+ virtual task generate_transaction();
+ transaction_init();
+ `DV_CHECK_RANDOMIZE_WITH_FATAL(transaction,num_segments == 2;)
+ endtask
+
+endclass : spi_host_error_cmd_vseq
diff --git a/hw/ip/spi_host/dv/env/seq_lib/spi_host_event_vseq.sv b/hw/ip/spi_host/dv/env/seq_lib/spi_host_event_vseq.sv
new file mode 100644
index 0000000..3994ab2
--- /dev/null
+++ b/hw/ip/spi_host/dv/env/seq_lib/spi_host_event_vseq.sv
@@ -0,0 +1,137 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// event test vseq
+// sequence verifies all events occur in event_enable register
+class spi_host_event_vseq extends spi_host_tx_rx_vseq;
+ `uvm_object_utils(spi_host_event_vseq)
+ `uvm_object_new
+
+ bit rx_drain;
+ bit [7:0] rxqd;
+ bit [7:0] txqd;
+ spi_segment_item segment;
+ spi_host_intr_state_t intr_state;
+ int segms_size;
+ int segms_words;
+ spi_host_command_t command[$];
+ spi_host_command_t command_snd;
+
+ // TODO - to be removed when issue #12262
+ constraint spi_config_regs_c {
+ // configopts regs
+ foreach (spi_config_regs.cpol[i]) {spi_config_regs.cpol[i] == 1'b0;}
+ foreach (spi_config_regs.cpha[i]) {spi_config_regs.cpha[i] == 1'b0;}
+ foreach (spi_config_regs.csnlead[i]) {
+ spi_config_regs.csnlead[i] == cfg.seq_cfg.host_spi_max_csn_latency;
+ }
+ foreach (spi_config_regs.csntrail[i]) {
+ spi_config_regs.csntrail[i] == cfg.seq_cfg.host_spi_max_csn_latency;
+ }
+ foreach (spi_config_regs.csnidle[i]) {
+ spi_config_regs.csnidle[i] == cfg.seq_cfg.host_spi_max_csn_latency;
+ }
+ foreach (spi_config_regs.clkdiv[i]) {
+ spi_config_regs.clkdiv[i] == cfg.seq_cfg.host_spi_max_clkdiv;
+ }
+ }
+
+ constraint spi_host_command_reg_c {
+ spi_host_command_reg.direction == Bidir;
+ spi_host_command_reg.mode == Standard;
+ }
+
+ virtual task body();
+ segms_size = 0;
+ segms_words = 0;
+ cfg.seq_cfg.host_spi_min_len = 4;
+ cfg.seq_cfg.host_spi_max_len = 4;
+ wait_ready_for_command();
+ program_spi_host_regs();
+ check_event(ral.status.ready, 1);
+
+ while (segms_words <= spi_host_ctrl_reg.tx_watermark) begin
+ gen_trans();
+ end
+ check_event(ral.status.txwm,0);
+ for (int i = 0; i < command.size(); i++) begin
+ command_snd = command[i];
+ snd_cmd(command_snd);
+ if(i == 0) check_event(ral.status.active, 1);
+ csr_rd(.ptr(ral.status.txqd), .value(txqd));
+ if (txqd < spi_host_ctrl_reg.tx_watermark) begin
+ check_event(ral.status.txwm, 1);
+ end
+ end
+ read_rx_fifo();
+ check_event(ral.status.txempty, 1);
+
+ cfg.clk_rst_vif.wait_clks(100);
+
+ fork
+ begin : isolation_fork
+ fork
+ start_reactive_seq();
+ join_none
+
+ begin
+ for (int i = 0; i < spi_host_ctrl_reg.rx_watermark; i++) begin
+ check_event(ral.status.rxwm, 0);
+ if (i < spi_host_ctrl_reg.rx_watermark -1) check_event(ral.status.rxwm, 0);
+ spi_send_trans(1);
+ csr_spinwait(.ptr(ral.status.txqd), .exp_data(0));
+ csr_spinwait(.ptr(ral.status.rxqd), .exp_data(i+1));
+ end
+ check_event(ral.status.rxwm, 1);
+ if (spi_host_ctrl_reg.rx_watermark > 0) read_rx_fifo();
+ for (int i = 0; i < SPI_HOST_RX_DEPTH; i++) begin
+ check_event(ral.status.rxfull, 0);
+ if (i < SPI_HOST_RX_DEPTH - 1) check_event(ral.status.rxfull, 0);
+ spi_send_trans(1);
+ csr_spinwait(.ptr(ral.status.txqd), .exp_data(0));
+ csr_spinwait(.ptr(ral.status.rxqd), .exp_data(i+1));
+ end
+ check_event(ral.status.rxfull, 1);
+ read_rx_fifo();
+ end
+
+ disable fork;
+ end
+ join
+ endtask : body
+
+ virtual task gen_trans();
+ generate_transaction();
+ segment = new();
+ while (transaction.segments.size() > 0) begin
+ segment = transaction.segments.pop_back();
+ if (segment.command_reg.direction != RxOnly) begin
+ segms_size = segment.spi_data.size() + segms_size;
+ segms_words = segms_size/4;
+ access_data_fifo(segment.spi_data, TxFifo);
+ end
+ command.push_back(segment.command_reg);
+ end
+ endtask
+
+ virtual task snd_cmd(spi_host_command_t command_snd);
+ wait_ready_for_command();
+ program_command_reg(command_snd);
+ wait_ready_for_command();
+ endtask
+
+ virtual task spi_send_trans(int num_transactions, bit wait_ready = 1'b1);
+ for (int n = 0; n < num_transactions; n++) begin
+ generate_transaction();
+ send_trans(transaction, wait_ready);
+ if (wait_ready) wait_ready_for_command();
+ end
+ endtask
+
+ virtual task generate_transaction();
+ transaction_init();
+ transaction.tx_only_weight = 0;
+ `DV_CHECK_RANDOMIZE_WITH_FATAL(transaction,num_segments == 1;cmd == ReadStd;)
+ endtask
+endclass : spi_host_event_vseq
diff --git a/hw/ip/spi_host/dv/env/seq_lib/spi_host_overflow_underflow_vseq.sv b/hw/ip/spi_host/dv/env/seq_lib/spi_host_overflow_underflow_vseq.sv
new file mode 100644
index 0000000..aa4fabc
--- /dev/null
+++ b/hw/ip/spi_host/dv/env/seq_lib/spi_host_overflow_underflow_vseq.sv
@@ -0,0 +1,95 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// error test vseq
+// empty read error underflow
+// write tx full fifo error overflow
+
+class spi_host_error_txrx_vseq extends spi_host_tx_rx_vseq;
+ `uvm_object_utils(spi_host_error_txrx_vseq)
+ `uvm_object_new
+
+ spi_segment_item segment;
+ int txfifo_ptr = 0;
+ int segms_size;
+
+constraint spi_config_regs_c {
+ // configopts regs
+ foreach (spi_config_regs.cpol[i]) {spi_config_regs.cpol[i] == 1'b0;}
+ foreach (spi_config_regs.cpha[i]) {spi_config_regs.cpha[i] == 1'b0;}
+ foreach (spi_config_regs.csnlead[i]) {
+ spi_config_regs.csnlead[i] == cfg.seq_cfg.host_spi_max_csn_latency;
+ }
+ foreach (spi_config_regs.csntrail[i]) {
+ spi_config_regs.csntrail[i] == cfg.seq_cfg.host_spi_max_csn_latency;
+ }
+ foreach (spi_config_regs.csnidle[i]) {
+ spi_config_regs.csnidle[i] == cfg.seq_cfg.host_spi_max_csn_latency;
+ }
+ foreach (spi_config_regs.clkdiv[i]) {
+ spi_config_regs.clkdiv[i] == cfg.seq_cfg.host_spi_max_clkdiv;
+ }
+ }
+
+ virtual task body();
+ bit [7:0] read_q[$];
+ bit [7:0] txqd;
+ spi_host_intr_state_t intr_state;
+
+ fork
+ begin : isolation_fork
+ fork
+ start_reactive_seq();
+ join_none
+ begin
+ wait_ready_for_command();
+ start_spi_host_trans(num_trans);
+ csr_spinwait(.ptr(ral.status.active), .exp_data(1'b0));
+ csr_spinwait(.ptr(ral.status.rxqd), .exp_data(8'h0));
+ cfg.clk_rst_vif.wait_clks(100);
+ end
+ disable fork;
+ end
+ begin
+ read_rx_fifo();
+ end
+ join
+
+ access_data_fifo(read_q, RxFifo, 1'b0); // attempting empty read error underflow
+ check_error(ral.error_status.underflow,1);
+
+ csr_wr(.ptr(ral.configopts[0].clkdiv), .value(16'h28)); // clk div set to 20
+ cfg.seq_cfg.host_spi_min_len = 4;
+ cfg.seq_cfg.host_spi_max_len = 4;
+ // loop for depth X no of bytes and 5 words short of SPI_HOST_TX_DEPTH
+ while(txfifo_ptr < ((SPI_HOST_TX_DEPTH*4)-4)) begin
+ segms_size = 0;
+ if(txfifo_ptr < ((SPI_HOST_TX_DEPTH*4)-4)) begin
+ check_error(ral.error_status.overflow, 0);
+ end else begin
+ check_error(ral.error_status.overflow, 1);
+ end
+ gen_txn_filltx();
+ txfifo_ptr = segms_size + txfifo_ptr;
+ `uvm_info(`gfn, $sformatf("\n txfifo_ptr Value %d",txfifo_ptr), UVM_LOW)
+ program_command_reg(segment.command_reg);
+ end // end while
+
+ gen_txn_filltx(0); // segsize not incremented
+ check_error(ral.error_status.overflow,1);
+ endtask : body
+
+ task gen_txn_filltx(bit do_seqsize_increase = 1);
+ generate_transaction();
+ segment = new();
+ while (transaction.segments.size() > 0) begin
+ segment = transaction.segments.pop_back();
+ if (segment.command_reg.direction != RxOnly) begin
+ if(do_seqsize_increase) segms_size = segment.spi_data.size() + segms_size;
+ access_data_fifo(segment.spi_data, TxFifo,1'b0); // write tx fifo to overflow
+ end
+ end
+ endtask:gen_txn_filltx
+
+endclass : spi_host_error_txrx_vseq
diff --git a/hw/ip/spi_host/dv/env/seq_lib/spi_host_passthrough_mode_vseq.sv b/hw/ip/spi_host/dv/env/seq_lib/spi_host_passthrough_mode_vseq.sv
new file mode 100644
index 0000000..c289fa6
--- /dev/null
+++ b/hw/ip/spi_host/dv/env/seq_lib/spi_host_passthrough_mode_vseq.sv
@@ -0,0 +1,66 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// passthrough_mode test vseq
+// SPI_HOST HWIP Technical Specification Block Diagram
+class spi_host_passthrough_mode_vseq extends spi_host_tx_rx_vseq;
+ `uvm_object_utils(spi_host_passthrough_mode_vseq)
+ `uvm_object_new
+
+ virtual task pre_start();
+ cfg.en_scb = 0;
+ super.pre_start();
+ endtask
+
+ virtual task body();
+ bit en = 1'b1;
+ fork
+ begin
+ forever begin
+ if(!en) break;
+ @(posedge cfg.clk_rst_vif.clk);
+ if (cfg.spi_passthrough_vif.passthrough_en) begin
+ `DV_CHECK_EQ(cfg.spi_passthrough_vif.cio_sck_o, cfg.spi_passthrough_vif.sck)
+ `DV_CHECK_EQ(cfg.spi_passthrough_vif.cio_sck_en_o, cfg.spi_passthrough_vif.sck_en)
+ `DV_CHECK_EQ(cfg.spi_passthrough_vif.cio_csb_o, cfg.spi_passthrough_vif.csb)
+ `DV_CHECK_EQ(cfg.spi_passthrough_vif.cio_csb_en_o, cfg.spi_passthrough_vif.csb_en)
+ `DV_CHECK_EQ(cfg.spi_passthrough_vif.cio_sd_en_o, cfg.spi_passthrough_vif.s_en)
+ `DV_CHECK_EQ(cfg.spi_passthrough_vif.cio_sd_o, cfg.spi_passthrough_vif.is)
+ `DV_CHECK_EQ(cfg.spi_passthrough_vif.cio_sd_i, cfg.spi_passthrough_vif.os)
+ end else begin
+ `DV_CHECK_EQ(cfg.spi_passthrough_vif.cio_sck_o, 1'b0)
+ `DV_CHECK_EQ(cfg.spi_passthrough_vif.cio_sck_en_o, 1'b0)
+ `DV_CHECK_EQ(cfg.spi_passthrough_vif.cio_csb_o, 1'b1)
+ `DV_CHECK_EQ(cfg.spi_passthrough_vif.cio_csb_en_o, 1'b0)
+ `DV_CHECK_EQ(cfg.spi_passthrough_vif.cio_sd_en_o, 4'b0)
+ `DV_CHECK_EQ(cfg.spi_passthrough_vif.cio_sd_o, 4'b0)
+ `DV_CHECK_EQ(cfg.spi_passthrough_vif.os, 4'hf)
+ end
+ end
+ end
+ begin
+ while (en) begin
+ @(posedge cfg.clk_rst_vif.clk);
+ cfg.spi_passthrough_vif.sck_en <= $urandom_range(0, 1);
+ cfg.spi_passthrough_vif.csb_en <= $urandom_range(0, 1);
+ cfg.spi_passthrough_vif.s_en <= $urandom_range(0, 1);
+ cfg.spi_passthrough_vif.csb <= $urandom_range(0, 1);
+ cfg.spi_passthrough_vif.sck <= $urandom_range(0, 1);
+ cfg.spi_passthrough_vif.is <= $urandom_range(100, 2000);
+ cfg.spi_passthrough_vif.cio_sd_i <= $urandom_range(100, 2000);
+ end
+ cfg.clk_rst_vif.wait_clks($urandom_range(10, 20));
+ end
+ begin
+ @(posedge cfg.clk_rst_vif.clk);
+ for (int i = 0; i < (num_trans*num_runs); i++) begin
+ @(posedge cfg.clk_rst_vif.clk);
+ cfg.spi_passthrough_vif.passthrough_en <= $urandom_range(0, 1);
+ cfg.clk_rst_vif.wait_clks($urandom_range(100, 200));
+ end
+ en = 1'b0;
+ end
+ join
+ endtask : body
+endclass : spi_host_passthrough_mode_vseq
diff --git a/hw/ip/spi_host/dv/env/seq_lib/spi_host_performance_vseq.sv b/hw/ip/spi_host/dv/env/seq_lib/spi_host_performance_vseq.sv
index f795acb..24b98d5 100644
--- a/hw/ip/spi_host/dv/env/seq_lib/spi_host_performance_vseq.sv
+++ b/hw/ip/spi_host/dv/env/seq_lib/spi_host_performance_vseq.sv
@@ -35,11 +35,8 @@
virtual task start_spi_host_trans(int num_transactions, bit wait_ready = 1'b1);
cfg.seq_cfg.std_en = 1;
- //TODO: enable dual_en and quad_en
- cfg.seq_cfg.dual_en = 0;
- cfg.seq_cfg.quad_en = 0;
+ cfg.seq_cfg.dual_en = 1;
+ cfg.seq_cfg.quad_en = 1;
super.start_spi_host_trans(num_trans);
endtask
-
endclass : spi_host_performance_vseq
-
diff --git a/hw/ip/spi_host/dv/env/seq_lib/spi_host_stress_all_vseq.sv b/hw/ip/spi_host/dv/env/seq_lib/spi_host_stress_all_vseq.sv
new file mode 100644
index 0000000..601587e
--- /dev/null
+++ b/hw/ip/spi_host/dv/env/seq_lib/spi_host_stress_all_vseq.sv
@@ -0,0 +1,44 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// sw_reset test vseq
+class spi_host_stress_all_vseq extends spi_host_base_vseq;
+ `uvm_object_utils(spi_host_stress_all_vseq)
+ `uvm_object_new
+
+ constraint num_trans_c {
+ num_trans inside {[3:6]};
+ }
+
+
+ virtual task body();
+ string seq_names[] = {"spi_host_smoke_vseq",
+ "spi_host_speed_vseq",
+ "spi_host_performance_vseq",
+ "spi_host_event_vseq",
+ "spi_host_overflow_underflow_vseq",
+ "spi_host_sw_reset_vseq"};
+
+ for (int i = 1; i <= num_trans; i++) begin
+ uvm_sequence seq;
+ spi_host_base_vseq spi_host_vseq;
+ uint seq_idx = $urandom_range(0, seq_names.size - 1);
+
+ seq = create_seq_by_name(seq_names[seq_idx]);
+ `downcast(spi_host_vseq, seq)
+
+ // if upper seq disables do_apply_reset for this seq, then can't issue reset
+ // as upper seq may drive reset
+ if (do_apply_reset) spi_host_vseq.do_apply_reset = $urandom_range(0, 1);
+ else spi_host_vseq.do_apply_reset = 0;
+
+ spi_host_vseq.set_sequencer(p_sequencer);
+ `DV_CHECK_RANDOMIZE_FATAL(spi_host_vseq)
+
+ spi_host_vseq.start(p_sequencer);
+ end
+
+ endtask : body
+
+endclass : spi_host_stress_all_vseq
diff --git a/hw/ip/spi_host/dv/env/seq_lib/spi_host_sw_reset_vseq.sv b/hw/ip/spi_host/dv/env/seq_lib/spi_host_sw_reset_vseq.sv
index a259fa2..85e3011 100644
--- a/hw/ip/spi_host/dv/env/seq_lib/spi_host_sw_reset_vseq.sv
+++ b/hw/ip/spi_host/dv/env/seq_lib/spi_host_sw_reset_vseq.sv
@@ -35,13 +35,12 @@
read_rx_fifo();
end
join
-
+
txfifo_fill();
cfg.clk_rst_vif.wait_clks($urandom_range(100,200));
spi_host_init();
cfg.clk_rst_vif.wait_clks($urandom_range(100,200));
-
csr_rd_check(.ptr(ral.status.rxempty), .compare_value(1'b1));
csr_rd_check(.ptr(ral.status.txempty), .compare_value(1'b1));
end // end for loop
diff --git a/hw/ip/spi_host/dv/env/seq_lib/spi_host_tx_rx_vseq.sv b/hw/ip/spi_host/dv/env/seq_lib/spi_host_tx_rx_vseq.sv
index 0d3817b..96de07b 100644
--- a/hw/ip/spi_host/dv/env/seq_lib/spi_host_tx_rx_vseq.sv
+++ b/hw/ip/spi_host/dv/env/seq_lib/spi_host_tx_rx_vseq.sv
@@ -23,8 +23,6 @@
program_spi_host_regs();
if (wait_ready) wait_ready_for_command();
csr_rd(.ptr(ral.status), .value(status));
- cfg.seq_cfg.host_spi_min_len = 4;
- cfg.seq_cfg.host_spi_max_len = 16;
for (int n = 0; n < num_transactions; n++) begin
generate_transaction();
@@ -92,4 +90,33 @@
`DV_CHECK_RANDOMIZE_FATAL(transaction)
endtask
+ task check_event(uvm_reg_field fld, bit value);
+ spi_host_intr_state_t intr_state;
+ uvm_reg_field enable_fld;
+ if (fld == ral.status.active) begin
+ enable_fld = ral.event_enable.get_field_by_name("idle");
+ end
+ else begin
+ enable_fld = ral.event_enable.get_field_by_name(fld.get_name);
+ end
+ csr_rd_check(.ptr(fld), .compare_value(value));
+ if (enable_fld != null) begin
+ bit enable = `gmv(enable_fld);
+ check_interrupts(1 << intr_state.spi_event, value & enable);
+ end else begin
+ check_interrupts(1 << intr_state.spi_event, 0);
+ end
+ endtask
+
+ task check_error(uvm_reg_field fld, bit value);
+ spi_host_intr_state_t intr_state;
+ uvm_reg_field enable_fld = ral.error_enable.get_field_by_name(fld.get_name);
+ csr_rd_check(.ptr(fld), .compare_value(value));
+ if (enable_fld != null) begin
+ bit enable = `gmv(enable_fld);
+ check_interrupts(1 << intr_state.error, value & enable);
+ end else begin
+ check_interrupts(1 << intr_state.error, 0);
+ end
+ endtask
endclass : spi_host_tx_rx_vseq
diff --git a/hw/ip/spi_host/dv/env/seq_lib/spi_host_vseq_list.sv b/hw/ip/spi_host/dv/env/seq_lib/spi_host_vseq_list.sv
index 8b6fc6f..d8ec992 100644
--- a/hw/ip/spi_host/dv/env/seq_lib/spi_host_vseq_list.sv
+++ b/hw/ip/spi_host/dv/env/seq_lib/spi_host_vseq_list.sv
@@ -6,6 +6,11 @@
`include "spi_host_tx_rx_vseq.sv"
`include "spi_host_smoke_vseq.sv"
`include "spi_host_speed_vseq.sv"
+`include "spi_host_event_vseq.sv"
`include "spi_host_performance_vseq.sv"
`include "spi_host_sw_reset_vseq.sv"
+`include "spi_host_stress_all_vseq.sv"
+`include "spi_host_overflow_underflow_vseq.sv"
+`include "spi_host_error_cmd_vseq.sv"
+`include "spi_host_passthrough_mode_vseq.sv"
`include "spi_host_common_vseq.sv"
diff --git a/hw/ip/spi_host/dv/env/spi_host_env.core b/hw/ip/spi_host/dv/env/spi_host_env.core
index a5cf705..4f562c2 100644
--- a/hw/ip/spi_host/dv/env/spi_host_env.core
+++ b/hw/ip/spi_host/dv/env/spi_host_env.core
@@ -28,8 +28,13 @@
- seq_lib/spi_host_common_vseq.sv: {is_include_file: true}
- seq_lib/spi_host_smoke_vseq.sv: {is_include_file: true}
- seq_lib/spi_host_speed_vseq.sv: {is_include_file: true}
+ - seq_lib/spi_host_event_vseq.sv: {is_include_file: true}
- seq_lib/spi_host_performance_vseq.sv: {is_include_file: true}
- seq_lib/spi_host_sw_reset_vseq.sv: {is_include_file: true}
+ - seq_lib/spi_host_stress_all_vseq.sv: {is_include_file: true}
+ - seq_lib/spi_host_overflow_underflow_vseq.sv: {is_include_file: true}
+ - seq_lib/spi_host_error_cmd_vseq.sv: {is_include_file: true}
+ - seq_lib/spi_host_passthrough_mode_vseq.sv: {is_include_file: true}
file_type: systemVerilogSource
generate:
diff --git a/hw/ip/spi_host/dv/env/spi_host_scoreboard.sv b/hw/ip/spi_host/dv/env/spi_host_scoreboard.sv
index a8f24e0..5d68b77 100644
--- a/hw/ip/spi_host/dv/env/spi_host_scoreboard.sv
+++ b/hw/ip/spi_host/dv/env/spi_host_scoreboard.sv
@@ -318,6 +318,7 @@
bit [TL_DW-1:0] intr_en = `gmv(ral.intr_enable);
bit [NumSpiHostIntr-1:0] intr_exp = item.a_data | `gmv(ral.intr_state);
void'(ral.intr_state.predict(.value(intr_exp), .kind(UVM_PREDICT_DIRECT)));
+ // sample coverage
if (cfg.en_cov) begin
foreach (intr_exp[i]) begin
cov.intr_test_cg.sample(i, item.a_data[i], intr_en[i], intr_exp[i]);
@@ -390,17 +391,17 @@
if (data_phase_read) begin
case (csr_name)
"intr_state": begin
- spi_intr_state_reg.spi_event = bit'(get_field_val(ral.intr_state.spi_event,
- item.a_data));
- spi_intr_state_reg.error = bit'(get_field_val(ral.intr_state.error, item.a_data));
- if (cfg.en_cov) begin
- bit [TL_DW-1:0] intr_en = `gmv(ral.intr_enable);
- bit [NumSpiHostIntr-1:0] intr_exp = `gmv(ral.intr_state);
+ spi_intr_state_reg.spi_event = bit'(get_field_val(ral.intr_state.spi_event,
+ item.a_data));
+ spi_intr_state_reg.error = bit'(get_field_val(ral.intr_state.error, item.a_data));
+ if (cfg.en_cov) begin
+ bit [TL_DW-1:0] intr_en = `gmv(ral.intr_enable);
+ bit [NumSpiHostIntr-1:0] intr_exp = `gmv(ral.intr_state);
foreach (intr_exp[i]) begin
cov.intr_cg.sample(i, intr_en[i], item.d_data);
cov.intr_pins_cg.sample(i, cfg.intr_vif.pins[i]);
end
- end
+ end
end
"error_status": begin
spi_error_status_reg.accessinval = bit'(get_field_val(ral.error_status.accessinval,
@@ -453,7 +454,7 @@
`DV_EOT_PRINT_Q_CONTENTS(spi_segment_item, read_segment_q)
`DV_EOT_PRINT_TLM_FIFO_CONTENTS(spi_item, host_data_fifo)
`DV_EOT_PRINT_TLM_FIFO_CONTENTS(spi_item, device_data_fifo)
- if ((rx_data_q.size() != 0))
+ if((rx_data_q.size() != 0))
`uvm_fatal(`gfn, $sformatf("ERROR - RX FIFO in DUT still has data to be read!"))
endfunction : check_phase
diff --git a/hw/ip/spi_host/dv/env/spi_passthrough_if.sv b/hw/ip/spi_host/dv/env/spi_passthrough_if.sv
index 25cc270..e654793 100644
--- a/hw/ip/spi_host/dv/env/spi_passthrough_if.sv
+++ b/hw/ip/spi_host/dv/env/spi_passthrough_if.sv
@@ -15,7 +15,12 @@
bit [3:0] is;
bit [3:0] os;
bit [3:0] s_en;
- logic [3:0] cio_sd_o;
- bit [3:0] cio_sd_i;
+ bit cio_sck_o;
+ bit cio_sck_en_o;
+ bit cio_csb_o;
+ bit cio_csb_en_o;
+ bit [3:0] cio_sd_o;
+ bit [3:0] cio_sd_en_o;
+ bit [3:0] cio_sd_i;
endinterface : spi_passthrough_if
diff --git a/hw/ip/spi_host/dv/spi_host_sim_cfg.hjson b/hw/ip/spi_host/dv/spi_host_sim_cfg.hjson
index 17a21e6..11e2060 100644
--- a/hw/ip/spi_host/dv/spi_host_sim_cfg.hjson
+++ b/hw/ip/spi_host/dv/spi_host_sim_cfg.hjson
@@ -80,6 +80,30 @@
name: spi_host_sw_reset
uvm_test_seq: spi_host_sw_reset_vseq
}
+ {
+ name: spi_host_overflow_underflow
+ uvm_test_seq: spi_host_overflow_underflow_vseq
+ run_opts: ["+en_scb=0"]
+ }
+ {
+ name: spi_host_error_cmd
+ uvm_test_seq: spi_host_error_cmd_vseq
+ run_opts: ["+en_scb=0"]
+ }
+ {
+ name: spi_host_event
+ uvm_test_seq: spi_host_event_vseq
+ run_opts: ["+en_scb=0", "+test_timeout_ns=1_000_000_000"]
+ }
+ {
+ name: spi_host_stress_all
+ uvm_test_seq: spi_host_stress_all_vseq
+ }
+ {
+ name: spi_host_passthrough_mode
+ uvm_test_seq: spi_host_passthrough_mode_vseq
+ run_opts: ["+en_scb=0"]
+ }
// TODO: add more tests here
]
diff --git a/hw/ip/spi_host/dv/tb.sv b/hw/ip/spi_host/dv/tb.sv
index c0876b5..7d9da96 100644
--- a/hw/ip/spi_host/dv/tb.sv
+++ b/hw/ip/spi_host/dv/tb.sv
@@ -76,28 +76,23 @@
.intr_spi_event_o (intr_event)
);
- assign passthrough_i.sck = clk;
- always_ff @(posedge clk or negedge rst_n) begin
- if (!rst_n) begin
- passthrough_i.passthrough_en <= 1'b0;
- passthrough_i.sck_en <= 1'b0;
- passthrough_i.csb_en <= 1'b0;
- passthrough_i.s_en <= 1'b0;
- passthrough_i.csb <= 1'b1;
- end else begin
- passthrough_i.passthrough_en <= spi_passthrough_if.passthrough_en;
- passthrough_i.sck_en <= spi_passthrough_if.sck_en;
- passthrough_i.csb_en <= spi_passthrough_if.csb_en;
- passthrough_i.s_en <= spi_passthrough_if.s_en;
- passthrough_i.csb <= spi_passthrough_if.csb;
- end
- end
+ assign passthrough_i.passthrough_en = spi_passthrough_if.passthrough_en;
+ assign passthrough_i.sck_en = spi_passthrough_if.sck_en;
+ assign passthrough_i.csb_en = spi_passthrough_if.csb_en;
+ assign passthrough_i.s_en = spi_passthrough_if.s_en;
+ assign passthrough_i.csb = spi_passthrough_if.csb;
+ assign passthrough_i.sck = spi_passthrough_if.sck;
- assign passthrough_i.s = spi_passthrough_if.is;
- assign spi_passthrough_if.os = passthrough_o.s;
- assign spi_passthrough_if.cio_sd_o = cio_sd_o;
+ assign passthrough_i.s = spi_passthrough_if.is;
+ assign spi_passthrough_if.os = passthrough_o.s;
+ assign spi_passthrough_if.cio_sck_o = cio_sck_o;
+ assign spi_passthrough_if.cio_sck_en_o = cio_sck_en_o;
+ assign spi_passthrough_if.cio_csb_o = cio_csb_o;
+ assign spi_passthrough_if.cio_csb_en_o = cio_csb_en_o;
+ assign spi_passthrough_if.cio_sd_en_o = cio_sd_en_o;
+ assign spi_passthrough_if.cio_sd_o = cio_sd_o;
- assign cio_sd_i = spi_passthrough_if.passthrough_en ? spi_passthrough_if.cio_sd_i : si_pulldown;
+ assign cio_sd_i = spi_passthrough_if.passthrough_en ? spi_passthrough_if.cio_sd_i : si_pulldown;
// configure spi_if i/o
assign spi_if.sck = (cio_sck_en_o) ? cio_sck_o : 1'bz;
