[top] First draft PR to enlarge memories

- Enlarge memories to include ECC
- Disable parity generation
- tlul_adapter level and above still assume previous width
- Follow-on PR will introduce more changes upstream

Signed-off-by: Timothy Chen <timothytim@google.com>

hw/top_earlgrey/data/top_earlgrey.hjson

diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
index 78cfabd..fb9a27b 100755
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -539,7 +539,9 @@
       type: "rom",
       base_addr: "0x00008000",
       swaccess: "ro",
-      size: "0x4000"
+      size: "0x4000",
+      // data integrity width
+      integ_width: 7,
       inter_signal_list: [
         { struct: "tl"
           package: "tlul_pkg"
@@ -557,6 +559,8 @@
       base_addr: "0x10000000",
       size: "0x20000",
       byte_write: "true",
+      // data integrity width
+      integ_width: 7,
       exec: "1",
       inter_signal_list: [
         { struct: "tl"
@@ -589,6 +593,8 @@
       base_addr: "0x40600000",
       size: "0x1000",
       byte_write: "true",
+      // data integrity width
+      integ_width: 7,
       exec: "0",
       inter_signal_list: [
         { struct: "tl"