[flash_ctrl] Remove scramble for english_breakfast
- allow flash scramble to be removed for cw305 to give some
fpga breathing space
- the parameter is a Sec parameter that should be double
checked prior to tapeout
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.hjson b/hw/ip/flash_ctrl/data/flash_ctrl.hjson
index 57f7fa3..03922b5 100644
--- a/hw/ip/flash_ctrl/data/flash_ctrl.hjson
+++ b/hw/ip/flash_ctrl/data/flash_ctrl.hjson
@@ -384,6 +384,14 @@
default: "2724870391",
local: "true"
},
+
+ { name: "SecScrambleEn",
+ desc: "Compile-time option to enable flash scrambling",
+ type: "bit",
+ default: "1",
+ local: "false",
+ expose: "true",
+ },
],
regwidth: "32",
diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.hjson.tpl b/hw/ip/flash_ctrl/data/flash_ctrl.hjson.tpl
index c89a6d4..f6aa5d4 100644
--- a/hw/ip/flash_ctrl/data/flash_ctrl.hjson.tpl
+++ b/hw/ip/flash_ctrl/data/flash_ctrl.hjson.tpl
@@ -381,6 +381,14 @@
default: "${int("0xa26a38f7", 16)}",
local: "true"
},
+
+ { name: "SecScrambleEn",
+ desc: "Compile-time option to enable flash scrambling",
+ type: "bit",
+ default: "1",
+ local: "false",
+ expose: "true",
+ },
],
regwidth: "32",
diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl b/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl
index 5702f02..0a4965c 100644
--- a/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl
+++ b/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl
@@ -16,7 +16,8 @@
parameter flash_key_t RndCnstAddrKey = RndCnstAddrKeyDefault,
parameter flash_key_t RndCnstDataKey = RndCnstDataKeyDefault,
parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault,
- parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault
+ parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault,
+ parameter bit SecScrambleEn = 1'b1
) (
input clk_i,
input rst_ni,
@@ -1150,7 +1151,9 @@
.rerror_i ({flash_host_rderr,1'b0})
);
- flash_phy u_eflash (
+ flash_phy #(
+ .SecScrambleEn(SecScrambleEn)
+ ) u_eflash (
.clk_i,
.rst_ni,
.host_req_i (flash_host_req),
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
index 1c142da..ac819ca 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
@@ -16,7 +16,8 @@
parameter flash_key_t RndCnstAddrKey = RndCnstAddrKeyDefault,
parameter flash_key_t RndCnstDataKey = RndCnstDataKeyDefault,
parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault,
- parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault
+ parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault,
+ parameter bit SecScrambleEn = 1'b1
) (
input clk_i,
input rst_ni,
@@ -1151,7 +1152,9 @@
.rerror_i ({flash_host_rderr,1'b0})
);
- flash_phy u_eflash (
+ flash_phy #(
+ .SecScrambleEn(SecScrambleEn)
+ ) u_eflash (
.clk_i,
.rst_ni,
.host_req_i (flash_host_req),
diff --git a/hw/ip/flash_ctrl/rtl/flash_phy.sv b/hw/ip/flash_ctrl/rtl/flash_phy.sv
index 07111c8..6224eed 100644
--- a/hw/ip/flash_ctrl/rtl/flash_phy.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_phy.sv
@@ -13,7 +13,9 @@
module flash_phy
import flash_ctrl_pkg::*;
import prim_mubi_pkg::mubi4_t;
-
+#(
+ parameter bit SecScrambleEn = 1'b1
+)
(
input clk_i,
input rst_ni,
@@ -211,7 +213,9 @@
assign ctrl_req = flash_ctrl_i.req & (ctrl_bank_sel == bank);
assign ecc_addr[bank][BusBankAddrW +: BankW] = bank;
- flash_phy_core u_core (
+ flash_phy_core #(
+ .SecScrambleEn(SecScrambleEn)
+ ) u_core (
.clk_i,
.rst_ni,
// integrity error is either from host or from controller
diff --git a/hw/ip/flash_ctrl/rtl/flash_phy_core.sv b/hw/ip/flash_ctrl/rtl/flash_phy_core.sv
index 4c334f1..d5a922e 100644
--- a/hw/ip/flash_ctrl/rtl/flash_phy_core.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_phy_core.sv
@@ -12,7 +12,8 @@
import flash_phy_pkg::*;
import prim_mubi_pkg::mubi4_t;
#(
- parameter int unsigned ArbCnt = 4
+ parameter int unsigned ArbCnt = 4,
+ parameter bit SecScrambleEn = 1'b1
) (
input clk_i,
input rst_ni,
@@ -376,7 +377,9 @@
rd_calc_addr;
// SEC_CM: MEM.SCRAMBLE
- flash_phy_scramble u_scramble (
+ flash_phy_scramble #(
+ .SecScrambleEn(SecScrambleEn)
+ ) u_scramble (
.clk_i,
.rst_ni,
// both escalation and and integrity error cause the scramble keys to change
diff --git a/hw/ip/flash_ctrl/rtl/flash_phy_scramble.sv b/hw/ip/flash_ctrl/rtl/flash_phy_scramble.sv
index 4c6590d..062e06e 100644
--- a/hw/ip/flash_ctrl/rtl/flash_phy_scramble.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_phy_scramble.sv
@@ -9,7 +9,9 @@
// in two and separately manipulated by the program and read pipelines.
//
-module flash_phy_scramble import flash_phy_pkg::*; (
+module flash_phy_scramble import flash_phy_pkg::*; #(
+ parameter bit SecScrambleEn = 1'b1
+) (
input clk_i,
input rst_ni,
input intg_err_i,
@@ -51,18 +53,33 @@
assign unused_key = muxed_addr_key[KeySize-1 -: UnusedWidth];
// Galois Multiply portion
- prim_gf_mult # (
- .Width(DataWidth),
- .StagesPerCycle(DataWidth / GfMultCycles)
- ) u_mult (
- .clk_i,
- .rst_ni,
- .req_i(calc_req_i),
- .operand_a_i({muxed_addr_key[DataWidth +: AddrPadWidth], addr_i}),
- .operand_b_i(muxed_addr_key[DataWidth-1:0]),
- .ack_o(calc_ack_o),
- .prod_o(mask_o)
- );
+ if (SecScrambleEn) begin : gen_gf_mult
+ prim_gf_mult # (
+ .Width(DataWidth),
+ .StagesPerCycle(DataWidth / GfMultCycles)
+ ) u_mult (
+ .clk_i,
+ .rst_ni,
+ .req_i(calc_req_i),
+ .operand_a_i({muxed_addr_key[DataWidth +: AddrPadWidth], addr_i}),
+ .operand_b_i(muxed_addr_key[DataWidth-1:0]),
+ .ack_o(calc_ack_o),
+ .prod_o(mask_o)
+ );
+ end else begin : gen_no_gf_mult
+ assign mask_o = '0;
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ calc_ack_o <= '0;
+ end else if (calc_req_i && calc_ack_o) begin
+ calc_ack_o <= '0;
+ end else if (calc_req_i && !calc_ack_o) begin
+ calc_ack_o <= '1;
+ end
+ end
+ end
+
// Cipher portion
logic dec;
@@ -100,25 +117,37 @@
assign cipher_valid_in_d = op_ack_o ? '0 : op_req_i & !cipher_valid_out;
assign op_ack_o = cipher_valid_in_q & cipher_valid_out;
- prim_prince # (
- .DataWidth(DataWidth),
- .KeyWidth(KeySize),
- // Use improved key schedule proposed by https://eprint.iacr.org/2014/656.pdf (see appendix).
- .UseOldKeySched(1'b0),
- .HalfwayDataReg(1'b1),
- // No key register is needed half way, since the data_key_i and operation op_type_i inputs
- // remain constant until one data block has been processed.
- .HalfwayKeyReg (1'b0)
- ) u_cipher (
- .clk_i,
- .rst_ni,
- .valid_i(cipher_valid_in_d),
- .data_i(dec ? scrambled_data_i : plain_data_i),
- .key_i(data_key_sel ? rand_data_key_i : data_key_i),
- .dec_i(dec),
- .data_o(data),
- .valid_o(cipher_valid_out)
- );
+ if (SecScrambleEn) begin : gen_prince
+ prim_prince # (
+ .DataWidth(DataWidth),
+ .KeyWidth(KeySize),
+ // Use improved key schedule proposed by https://eprint.iacr.org/2014/656.pdf (see appendix).
+ .UseOldKeySched(1'b0),
+ .HalfwayDataReg(1'b1),
+ // No key register is needed half way, since the data_key_i and operation op_type_i inputs
+ // remain constant until one data block has been processed.
+ .HalfwayKeyReg (1'b0)
+ ) u_cipher (
+ .clk_i,
+ .rst_ni,
+ .valid_i(cipher_valid_in_d),
+ .data_i(dec ? scrambled_data_i : plain_data_i),
+ .key_i(data_key_sel ? rand_data_key_i : data_key_i),
+ .dec_i(dec),
+ .data_o(data),
+ .valid_o(cipher_valid_out)
+ );
+
+ end else begin : gen_no_prince
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ cipher_valid_out <= '0;
+ end else begin
+ cipher_valid_out <= cipher_valid_in_d;
+ end
+ end
+ assign data = dec ? scrambled_data_i : plain_data_i;
+ end
// if decrypt, output the unscrambled data, feed input through otherwise
assign plain_data_o = dec ? data : scrambled_data_i;
@@ -127,4 +156,5 @@
assign scrambled_data_o = dec ? plain_data_i : data;
+
endmodule // flash_phy_scramble
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 2ce7efe..a4a57ca 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -4456,6 +4456,14 @@
default: 0x3480d1896c7ff9ed5941bd125c6eb18772e220f3
randwidth: 160
}
+ {
+ name: SecScrambleEn
+ desc: Compile-time option to enable flash scrambling
+ type: bit
+ default: "1"
+ expose: "true"
+ name_top: SecFlashCtrlScrambleEn
+ }
]
inter_signal_list:
[
diff --git a/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson b/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson
index ab6b034..1b41eaf 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson
+++ b/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson
@@ -390,6 +390,14 @@
default: "2724870391",
local: "true"
},
+
+ { name: "SecScrambleEn",
+ desc: "Compile-time option to enable flash scrambling",
+ type: "bit",
+ default: "1",
+ local: "false",
+ expose: "true",
+ },
],
regwidth: "32",
diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
index 1285687..c15fa4a 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
@@ -22,7 +22,8 @@
parameter flash_key_t RndCnstAddrKey = RndCnstAddrKeyDefault,
parameter flash_key_t RndCnstDataKey = RndCnstDataKeyDefault,
parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault,
- parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault
+ parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault,
+ parameter bit SecScrambleEn = 1'b1
) (
input clk_i,
input rst_ni,
@@ -1157,7 +1158,9 @@
.rerror_i ({flash_host_rderr,1'b0})
);
- flash_phy u_eflash (
+ flash_phy #(
+ .SecScrambleEn(SecScrambleEn)
+ ) u_eflash (
.clk_i,
.rst_ni,
.host_req_i (flash_host_req),
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 40fc6b7..5973dc3 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -48,6 +48,7 @@
// parameters for sram_ctrl_ret_aon
parameter bit SramCtrlRetAonInstrExec = 0,
// parameters for flash_ctrl
+ parameter bit SecFlashCtrlScrambleEn = 1,
// parameters for rv_dm
parameter logic [31:0] RvDmIdcodeValue = 32'h 0000_0001,
// parameters for rv_plic
@@ -2029,7 +2030,8 @@
.RndCnstAddrKey(RndCnstFlashCtrlAddrKey),
.RndCnstDataKey(RndCnstFlashCtrlDataKey),
.RndCnstLfsrSeed(RndCnstFlashCtrlLfsrSeed),
- .RndCnstLfsrPerm(RndCnstFlashCtrlLfsrPerm)
+ .RndCnstLfsrPerm(RndCnstFlashCtrlLfsrPerm),
+ .SecScrambleEn(SecFlashCtrlScrambleEn)
) u_flash_ctrl (
// Input
diff --git a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
index 1fe6aa8..fea9fd6 100644
--- a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
+++ b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
@@ -360,6 +360,9 @@
clock_group: "infra",
reset_connections: {rst_ni: "lc", rst_otp_ni: "lc_io_div4"},
base_addrs: {core: "0x41000000", prim: "0x41008000", mem: "0x20000000"}
+ param_decl: {
+ SecScrambleEn: "0"
+ }
memory: {
mem: {
label: "eflash",
