| commit | 4547c427e32ad1cbabd4ec7504f921118b395415 | [log] [tgz] |
|---|---|---|
| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Thu Mar 18 11:53:04 2021 +0000 |
| committer | Rupert Swarbrick <rswarbrick@gmail.com> | Tue Mar 30 09:50:02 2021 +0100 |
| tree | 31d273306dbac8ab74ea6a69a96b58d8ca652f55 | |
| parent | 983e6641cb3968aae530922bf24021077e2c71f6 [diff] |
[dpi] Make an "ECC32" flavour of MemArea This will support memories that use a (39,32)-SECDED code. At the moment, it doesn't actually add the check bits (because we don't check them in our implementation yet), but it does lay everything out correctly. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
This repository contains hardware, software and utilities written as part of the OpenTitan project. It is structured as monolithic repository, or “monorepo”, where all components live in one repository. It exists to enable collaboration across partners participating in the OpenTitan project.
The project contains comprehensive documentation of all IPs and tools. You can access it online at docs.opentitan.org.
Have a look at CONTRIBUTING for guidelines on how to contribute code to this repository.
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).