| commit | 44824948d70eb0edd6eb6d71f6a3f2dc881136cd | [log] [tgz] |
|---|---|---|
| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Mon Dec 07 16:02:38 2020 +0000 |
| committer | Rupert Swarbrick <rswarbrick@gmail.com> | Wed Dec 09 08:22:10 2020 +0000 |
| tree | e3a17ea9aaf8bb5136f06038e063d3284d46b2b7 | |
| parent | 62f79b88c411e12b0df22a456d88f6862f342476 [diff] |
[otbn] Remove dependency on riscv-python-sim We were just using this for the Trace and TracePC classes, which contain almost nothing. Define our own Trace/TracePC classes, remove the "# type: ignore" hacks and fix the typing bugs that they hid. Finally define an explicit Trace.trace function, rather than relying on __str__ to generate trace output. We'll need this soon when we start comparing with the RTL (because we'll want a different format for different output types). Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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