[sensor_ctrl] Various updates to sensor_ctrl
- Based on recent nuvoton discussions
- Remove sensor_ctrl from always on domain
- Update sensor_ctrl alert event handling to assume async
- Remove 'ack modes' and replace with recoverable / fatal alerts
- Add software programming to categorize alerts into fatal or
recoverable
- Add wakeup function
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
index 7730a48..f570461 100644
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -440,11 +440,11 @@
base_addr: "0x40480000",
attr: "reggen_only",
},
- { name: "sensor_ctrl_aon",
+ { name: "sensor_ctrl",
type: "sensor_ctrl",
- clock_srcs: {clk_i: "io_div4"},
+ clock_srcs: {clk_i: "io_div4", clk_aon_i: "aon"},
clock_group: "secure",
- reset_connections: {rst_ni: "lc_io_div4"},
+ reset_connections: {rst_ni: "lc_io_div4", rst_aon_ni: "lc_aon"},
domain: ["Aon"],
base_addr: "0x40490000",
attr: "reggen_top",
@@ -922,10 +922,10 @@
'otp_ctrl.otp_ext_voltage_h' : 'otp_ext_voltage_h',
'otp_ctrl.otp_alert' : 'otp_alert',
'rstmgr_aon.por_n' : 'por_n'
- 'sensor_ctrl_aon.ast_alert' : 'sensor_ctrl_ast_alert',
- 'sensor_ctrl_aon.ast_status' : 'sensor_ctrl_ast_status',
- 'sensor_ctrl_aon.ast2pinmux' : 'ast2pinmux',
- 'sensor_ctrl_aon.ast_init_done' : 'ast_init_done',
+ 'sensor_ctrl.ast_alert' : 'sensor_ctrl_ast_alert',
+ 'sensor_ctrl.ast_status' : 'sensor_ctrl_ast_status',
+ 'sensor_ctrl.ast2pinmux' : 'ast2pinmux',
+ 'sensor_ctrl.ast_init_done' : 'ast_init_done',
'spi_device.sck_monitor' : 'sck_monitor',
'usbdev.usb_ref_val' : '',
'usbdev.usb_ref_pulse' : '',
@@ -1132,7 +1132,7 @@
{ instance: "pattgen", port: '', connection: 'muxed' , pad: '' , desc: ''},
{ instance: "spi_host1", port: '', connection: 'muxed' , pad: '' , desc: ''},
{ instance: "flash_ctrl", port: '', connection: 'muxed' , pad: '' , desc: ''},
- { instance: "sensor_ctrl_aon", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "sensor_ctrl", port: '', connection: 'muxed' , pad: '' , desc: ''},
{ instance: "pwm_aon", port: '', connection: 'muxed' , pad: '' , desc: ''},
{ instance: "otp_ctrl", port: 'test[0]', connection: 'muxed' , pad: '' , desc: ''},
// Sysrst ctrl has both muxed and dedicated IOs
diff --git a/hw/top_earlgrey/data/xbar_peri.hjson b/hw/top_earlgrey/data/xbar_peri.hjson
index 3f46641..a8e45de 100644
--- a/hw/top_earlgrey/data/xbar_peri.hjson
+++ b/hw/top_earlgrey/data/xbar_peri.hjson
@@ -147,7 +147,7 @@
reset: "rst_peri_ni",
pipeline: "false"
},
- { name: "sensor_ctrl_aon",
+ { name: "sensor_ctrl",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
@@ -201,7 +201,7 @@
"uart0", "uart1", "uart2", "uart3", "i2c0", "i2c1", "i2c2", "pattgen",
"gpio", "spi_device", "spi_host0", "spi_host1", "rv_timer", "usbdev",
"pwrmgr_aon", "rstmgr_aon", "clkmgr_aon", "pinmux_aon",
- "otp_ctrl.core", "otp_ctrl.prim", "lc_ctrl", "sensor_ctrl_aon",
+ "otp_ctrl.core", "otp_ctrl.prim", "lc_ctrl", "sensor_ctrl",
"alert_handler", "ast", "sram_ctrl_ret_aon.ram", "sram_ctrl_ret_aon.regs",
"aon_timer_aon", "adc_ctrl_aon", "sysrst_ctrl_aon", "pwm_aon"
],
diff --git a/hw/top_earlgrey/ip/sensor_ctrl/data/sensor_ctrl.hjson b/hw/top_earlgrey/ip/sensor_ctrl/data/sensor_ctrl.hjson
index c0bbe4d..6409293 100644
--- a/hw/top_earlgrey/ip/sensor_ctrl/data/sensor_ctrl.hjson
+++ b/hw/top_earlgrey/ip/sensor_ctrl/data/sensor_ctrl.hjson
@@ -9,7 +9,8 @@
#
{
name: "SENSOR_CTRL",
- clocking: [{clock: "clk_i", reset: "rst_ni"}],
+ clocking: [{clock: "clk_i", reset: "rst_ni", primary: true},
+ {clock: "clk_aon_i", reset: "rst_aon_ni"}],
bus_interfaces: [
{ protocol: "tlul", direction: "device" }
],
@@ -21,10 +22,22 @@
],
regwidth: "32",
param_list: [
- { name: "NumAlerts",
+ { name: "NumAlertEvents",
type: "int",
default: "13",
- desc: "Number of alerts",
+ desc: "Number of alert events from ast",
+ local: "true"
+ },
+ { name: "NumLocalEvents",
+ type: "int",
+ default: "1",
+ desc: "Number of local events",
+ local: "true"
+ },
+ { name: "NumAlerts",
+ type: "int",
+ default: "2",
+ desc: "Number of alerts sent from sensor control",
local: "true"
},
{ name: "NumIoRails",
@@ -35,46 +48,19 @@
},
],
+ wakeup_list: [
+ { name: "wkup_req",
+ desc: "Raised if an alert event is seen during low power"
+ },
+ ],
+
alert_list: [
- { name: "recov_as",
- desc: "Triggered through AST",
+ { name: "recov_alert",
+ desc: "recoverable sensor_ctrl alerts",
},
- { name: "recov_cg",
- desc: "Triggered through AST",
- },
- { name: "recov_gd",
- desc: "Triggered through AST",
- },
- { name: "recov_ts_hi",
- desc: "Triggered through AST",
- },
- { name: "recov_ts_lo",
- desc: "Triggered through AST",
- },
- { name: "recov_fla",
- desc: "Triggered through AST",
- },
- { name: "recov_otp",
- desc: "Triggered through AST",
- },
- { name: "recov_ot0",
- desc: "Triggered through AST",
- },
- { name: "recov_ot1",
- desc: "Triggered through AST",
- },
- { name: "recov_ot2",
- desc: "Triggered through AST",
- },
- { name: "recov_ot3",
- desc: "Triggered through AST",
- },
- { name: "recov_ot4",
- desc: "Triggered through AST",
- },
- { name: "recov_ot5",
- desc: "Triggered through AST",
- },
+ { name: "fatal_alert",
+ desc: "fatal sensor_ctrl alerts",
+ }
]
@@ -108,6 +94,13 @@
width: 9,
package: ""
},
+
+ { struct: "logic",
+ type: "uni",
+ name: "wkup_req",
+ act: "req",
+ package: ""
+ },
],
registers: [
@@ -115,7 +108,7 @@
swaccess: "rw0c",
hwaccess: "none",
desc: '''
- Controls the configurability of !!ACK_MODE register.
+ Controls the configurability of !!FATAL_ALERT_EN register.
''',
fields: [
@@ -131,33 +124,9 @@
{ multireg: {
cname: "SENSOR_CTRL",
- name: "ACK_MODE",
- desc: "Alert acknowledge mode",
- count: "NumAlerts",
- swaccess: "rw",
- hwaccess: "hro",
- regwen: "CFG_REGWEN",
- fields: [
- { bits: "1:0",
- name: "VAL",
- desc: '''
- Acknowledge mode to alerts.
- 0 is immediate acknowledge, the hardware immediately acks an incoming alert.
- 1 is software acknowledge. Software must program the appropriate bit in !!ALERT_STATE to acknowledge the alert.
- 2 is no acknowledge. When in this mode, any alert will effectively be considered fatal to the system.
- 3 is not a valid selection, but behaves similarly to 2.
- ''',
- resval: "0"
- },
- ],
- },
- },
-
- { multireg: {
- cname: "SENSOR_CTRL",
name: "ALERT_TRIG",
desc: "Alert trigger test",
- count: "NumAlerts",
+ count: "NumAlertEvents",
swaccess: "rw",
hwaccess: "hro",
fields: [
@@ -179,18 +148,64 @@
{ multireg: {
cname: "SENSOR_CTRL",
- name: "ALERT_STATE",
+ name: "FATAL_ALERT_EN",
+ regwen: "CFG_REGWEN",
desc: '''
- A bit is set whenever there is an incoming alert event.
- Software reads back the alert that was set and clears the appropriate bits to acknowledge the alert.
-
- This is only valid when !!ACK_MODE is set to software.
- For bit mapping, please see !!ALERT_TEST
+ Each bit represents that a corresponding alert is marked fatal instead of
+ recoverable
''',
- count: "NumAlerts",
+ count: "NumAlertEvents",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "0",
+ name: "VAL",
+ desc: '''
+ 1 - An alert event is fatal.
+ 0 - An alert event is recoverable.
+ ''',
+ resval: "0"
+ },
+ ],
+ },
+ },
+
+ { multireg: {
+ cname: "SENSOR_CTRL",
+ name: "RECOV_ALERT",
+ desc: '''
+ Each bit represents that a recoverable alert has been triggered by Ast.
+ Since these are recoverable alerts, they can be cleared by software.
+ ''',
+ count: "NumAlertEvents",
swaccess: "rw1c",
hwaccess: "hrw",
- hwqe: "true",
+ fields: [
+ { bits: "0",
+ name: "VAL",
+ desc: '''
+ 1 - An alert event has been set
+ 0 - No alert event has been set
+ ''',
+ resval: "0"
+ },
+ ],
+ },
+ },
+
+ { multireg: {
+ cname: "SENSOR_CTRL",
+ name: "FATAL_ALERT",
+ desc: '''
+ Each bit represents that a fatal alert has been triggered by Ast.
+ Since these registers represent fatal alerts, they cannot be cleared.
+
+ The lower bits are used for ast alert events.
+ The upper bits are used for local events.
+ ''',
+ count: "NumAlertEvents+NumLocalEvents",
+ swaccess: "ro",
+ hwaccess: "hrw",
fields: [
{ bits: "0",
name: "VAL",
diff --git a/hw/top_earlgrey/ip/sensor_ctrl/doc/_index.md b/hw/top_earlgrey/ip/sensor_ctrl/doc/_index.md
index 9c58f0f..31774dd 100644
--- a/hw/top_earlgrey/ip/sensor_ctrl/doc/_index.md
+++ b/hw/top_earlgrey/ip/sensor_ctrl/doc/_index.md
@@ -16,6 +16,7 @@
- Alert forwarding to `alert handler`
- Status readback for `analog sensor top`
- Pad debug hook up for `analog sensor top`
+- Wakeup based on alert events
# Theory of Operations
@@ -23,7 +24,7 @@
The diagram below shows how `sensor control` helps `analog sensor top` integration into the overall design.
-## Alert Handshake
+## Recoverable and Fatal Alerts
The `analog sensor top` sends alert requests in independent, differential form to the `sensor control`.
Each alert request consists of a pair of signals, one active high and one active low.
@@ -34,13 +35,21 @@
Once an alert request is detected as active, the `sensor control` then formulates a proper alert event through the `prim_alert_sender` and sends a notification to the `alert handler`.
The `sensor control` can optionally generate alert acknowledgements back to the `analog sensor top`.
-When an alert request is detected as active, the `sensor control` has 3 options after sending out the alert:
-- Do not acknowledge: Allow alerts to be continually triggered.
-- Software acknowledge: Let software decide whether an alert should stop triggering.
-- Hardware acknowledge. Let hardware immediately acknowledge the alert.
+For each incoming alert, it can be programmed as fatal or recoverable through {{< regref "FATAL_ALERT_EN" >}}.
+If set to recoverable, an alert will be registered in {{< regref "RECOV_ALERT" >}} and the original `analog sensor top` event acknowledged.
+The acknowledgement prevents alerts from constantly being sent.
-Once the `analog sensor top` receives the acknowledgment, it then drops the corresponding alert request.
+If set to fatal, an alert will be registered in {{< regref "FATAL_ALERT" >}} but the original `analog sensor top` event will not be acknowledged.
+This causes the alert to constantly send until the system escalates in some form.
+
+## Wakeup Requests
+
+In addition to forwarding events to the `alert handler`, incoming events can also be aggregated into a wakeup request to the system.
+The `sensor_ctrl` does not make assumptions about its power domains and thus it is up to the integrating system to decide which power modes allow alert event wakeups.
+
+As an example, if the `sensor_ctrl` is not placed in an always on domain, then it cannot send alert based wakeups if the system is in a deep low power state.
+It will only be able to send wakeups when the system is powered and the `clk_aon_i` input is available.
## Hardware Interfaces
diff --git a/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl.sv b/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl.sv
index 06f3fbb..b2bb164 100644
--- a/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl.sv
+++ b/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl.sv
@@ -15,6 +15,8 @@
// Primary module clocks
input clk_i,
input rst_ni,
+ input clk_aon_i,
+ input rst_aon_ni,
// Bus Interface
input tlul_pkg::tl_h2d_t tl_i,
@@ -33,18 +35,53 @@
// Alerts
input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
- output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o
+ output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,
+ // wakeup to power manager
+ output logic wkup_req_o
);
// The reg_pkg number of alerts and ast alerts must always match
- `ASSERT_INIT(NumAlertsMatch_A, ast_pkg::NumAlerts == NumAlerts)
+ `ASSERT_INIT(NumAlertsMatch_A, ast_pkg::NumAlerts == NumAlertEvents)
+
+ ///////////////////////////
+ // Incoming event synchronization - alerts can assert asynchronously
+ ///////////////////////////
+ logic [NumAlertEvents-1:0] async_alert_event_p, alert_event_p;
+ logic [NumAlertEvents-1:0] async_alert_event_n, alert_event_n;
+
+ for (genvar i = 0; i < NumAlertEvents; i++) begin : gen_alert_sync_assign
+ assign async_alert_event_p[i] = ast_alert_i.alerts[i].p;
+ assign async_alert_event_n[i] = ast_alert_i.alerts[i].n;
+ end
+
+ prim_flop_2sync #(
+ .Width(NumAlertEvents),
+ .ResetValue('0)
+ ) u_alert_p_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(async_alert_event_p),
+ .q_o(alert_event_p)
+ );
+
+ prim_flop_2sync #(
+ .Width(NumAlertEvents),
+ .ResetValue({NumAlertEvents{1'b1}})
+ ) u_alert_n_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(async_alert_event_n),
+ .q_o(alert_event_n)
+ );
+
///////////////////////////
// Register interface
///////////////////////////
sensor_ctrl_reg2hw_t reg2hw;
sensor_ctrl_hw2reg_t hw2reg;
+ logic intg_err;
sensor_ctrl_reg_top u_reg (
.clk_i,
@@ -53,7 +90,7 @@
.tl_o,
.reg2hw,
.hw2reg,
- .intg_err_o(),
+ .intg_err_o(intg_err),
.devmode_i(1'b1)
);
@@ -64,119 +101,159 @@
///////////////////////////
- // Alert handling
+ // Alert Event Handling
///////////////////////////
- logic [NumAlerts-1:0] alert_test;
- logic [NumAlerts-1:0] alerts_vld, alerts_clr;
- logic [NumAlerts-1:0] sw_ack_mode;
- logic [NumAlerts-1:0] no_ack_mode;
+ logic [NumAlertEvents-1:0] event_vld, event_clr;
// While the alerts are differential, they are not perfectly aligned.
// Instead, each alert is treated independently.
always_comb begin
- for (int i = 0; i < NumAlerts; i++) begin
- alerts_vld[i] = ast_alert_i.alerts[i].p | ~ast_alert_i.alerts[i].n;
+ for (int i = 0; i < NumAlertEvents; i++) begin
+ event_vld[i] = alert_event_p[i] | ~alert_event_n[i];
end
end
- // alert test connection
- assign alert_test[ast_pkg::AsSel] = reg2hw.alert_test.recov_as.qe &
- reg2hw.alert_test.recov_as.q;
- assign alert_test[ast_pkg::CgSel] = reg2hw.alert_test.recov_cg.qe &
- reg2hw.alert_test.recov_cg.q;
- assign alert_test[ast_pkg::GdSel] = reg2hw.alert_test.recov_gd.qe &
- reg2hw.alert_test.recov_gd.q;
- assign alert_test[ast_pkg::TsHiSel] = reg2hw.alert_test.recov_ts_hi.qe &
- reg2hw.alert_test.recov_ts_hi.q;
- assign alert_test[ast_pkg::TsLoSel] = reg2hw.alert_test.recov_ts_lo.qe &
- reg2hw.alert_test.recov_ts_lo.q;
- assign alert_test[ast_pkg::FlaSel] = reg2hw.alert_test.recov_fla.qe &
- reg2hw.alert_test.recov_fla.q;
- assign alert_test[ast_pkg::OtpSel] = reg2hw.alert_test.recov_otp.qe &
- reg2hw.alert_test.recov_otp.q;
- assign alert_test[ast_pkg::Ot0Sel] = reg2hw.alert_test.recov_ot0.qe &
- reg2hw.alert_test.recov_ot0.q;
- assign alert_test[ast_pkg::Ot1Sel] = reg2hw.alert_test.recov_ot1.qe &
- reg2hw.alert_test.recov_ot1.q;
- assign alert_test[ast_pkg::Ot2Sel] = reg2hw.alert_test.recov_ot2.qe &
- reg2hw.alert_test.recov_ot2.q;
- assign alert_test[ast_pkg::Ot3Sel] = reg2hw.alert_test.recov_ot3.qe &
- reg2hw.alert_test.recov_ot3.q;
- assign alert_test[ast_pkg::Ot4Sel] = reg2hw.alert_test.recov_ot4.qe &
- reg2hw.alert_test.recov_ot4.q;
- assign alert_test[ast_pkg::Ot5Sel] = reg2hw.alert_test.recov_ot5.qe &
- reg2hw.alert_test.recov_ot5.q;
-
-
- // fire an alert whenever indicated
- for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_senders
+ // Only recoverable alerts are ack'd. Fatal alerts are captured and continuously
+ // triggered, there is thus not a need to ever acknowledge the source.
+ // For recoverable alerts, the ack is only sent once the alert is captured into software readable
+ // registers
+ logic [NumAlertEvents-1:0] recov_event;
+ logic [NumAlertEvents-1:0] fatal_event;
+ for (genvar i = 0; i < NumAlertEvents; i++) begin : gen_ast_alert_events
// when there is a valid alert, set the alert state
- logic valid_alert;
+ assign recov_event[i] = event_vld[i] & ~reg2hw.fatal_alert_en[i];
+ assign fatal_event[i] = event_vld[i] & reg2hw.fatal_alert_en[i];
- assign sw_ack_mode[i] = ast_ack_mode_e'(reg2hw.ack_mode[i].q) == SwAck;
- assign no_ack_mode[i] = ast_ack_mode_e'(reg2hw.ack_mode[i].q) == NoAck |
- ast_ack_mode_e'(reg2hw.ack_mode[i].q) == InvalidAck;
+ assign hw2reg.recov_alert[i].d = 1'b1;
+ assign hw2reg.recov_alert[i].de = recov_event[i];
- // if differential checks fail, generate alert
- assign valid_alert = alerts_vld[i];
- assign hw2reg.alert_state[i].d = sw_ack_mode[i];
- assign hw2reg.alert_state[i].de = valid_alert;
+ assign hw2reg.fatal_alert[i].d = 1'b1;
+ assign hw2reg.fatal_alert[i].de = fatal_event[i];
- logic alert_req;
- logic alert_ack;
- assign alert_req = sw_ack_mode[i] ? reg2hw.alert_state[i].q : valid_alert;
+ // only recoverable alerts ack
+ assign event_clr[i] = recov_event[i] & reg2hw.recov_alert[i].q;
- prim_alert_sender #(
- .AsyncOn(AlertAsyncOn[i]),
- .IsFatal(0)
- ) u_prim_alert_sender (
- .clk_i,
- .rst_ni,
- .alert_test_i(alert_test[i]),
- .alert_req_i(alert_req),
- .alert_ack_o(alert_ack),
- .alert_state_o(),
- .alert_rx_i(alert_rx_i[i]),
- .alert_tx_o(alert_tx_o[i])
- );
-
- assign alerts_clr[i] = no_ack_mode[i] ? '0 :
- sw_ack_mode[i] ? reg2hw.alert_state[i].q & reg2hw.alert_state[i].qe :
- alert_req & alert_ack;
end
- // When in immediate ack mode, ack alerts as they are received by the sender
- // When in software ack mode, only ack when software issues the command to clear alert_state
- //
+ // handle internal alert events, currently only have fatals
+ for (genvar i = NumAlertEvents; i < TotalEvents; i++) begin : gen_local_alert_events
+ assign hw2reg.fatal_alert[i].d = 1'b1;
+ assign hw2reg.fatal_alert[i].de = intg_err;
+ end
+
// Note, even though the incoming alerts are differential, they are NOT expected to be
// consistent all the time. It is more appropriate for sensor_ctrl to treat them as
// independent lines.
- // As a result, the alerts_clr is only applied if an incoming alert is set to the active polarity.
+ // As a result, the alert_ack is only applied if an incoming alert is set to the active polarity.
//
- // Note, due to the converging nature of sensor ctrl (non-synced inputs being forwarded to 1
- // alert), it is possible that when one alert arrives, it is ack'd right when the differential
- // version comes. As a result, the first alert will be ack'd, and the second will also
- // immediately be ack'd, resulting in one alert being sent.
- // This is OK because the intent is to send the alert anyways, and the ack would not have happened
- // if the alert was not sent out. If the incoming alert stays high, then alerts will continue to
- // fire.
+
always_comb begin
- for (int i = 0; i < NumAlerts; i++) begin
- ast_alert_o.alerts_ack[i].p = ast_alert_i.alerts[i].p & alerts_clr[i];
- ast_alert_o.alerts_ack[i].n = ~(~ast_alert_i.alerts[i].n & alerts_clr[i]);
+ for (int i = 0; i < NumAlertEvents; i++) begin
+ ast_alert_o.alerts_ack[i].p = alert_event_p[i] & event_clr[i];
+ ast_alert_o.alerts_ack[i].n = ~(~alert_event_n[i] & event_clr[i]);
end
end
// alert trigger for test
always_comb begin
- for (int i = 0; i < NumAlerts; i++) begin
+ for (int i = 0; i < NumAlertEvents; i++) begin
ast_alert_o.alerts_trig[i].p = reg2hw.alert_trig[i];
ast_alert_o.alerts_trig[i].n = ~reg2hw.alert_trig[i];
end
end
+
+ // alert test connection
+ logic [NumAlerts-1:0] alert_test;
+ assign alert_test[RecovAlert] = reg2hw.alert_test.recov_alert.qe &
+ reg2hw.alert_test.recov_alert.q;
+ assign alert_test[FatalAlert] = reg2hw.alert_test.fatal_alert.qe &
+ reg2hw.alert_test.fatal_alert.q;
+
+ prim_alert_sender #(
+ .AsyncOn(AlertAsyncOn[RecovAlert]),
+ .IsFatal(0)
+ ) u_prim_recov_alert_sender (
+ .clk_i,
+ .rst_ni,
+ .alert_test_i(alert_test[RecovAlert]),
+ .alert_req_i(|recov_event),
+ .alert_ack_o(),
+ .alert_state_o(),
+ .alert_rx_i(alert_rx_i[RecovAlert]),
+ .alert_tx_o(alert_tx_o[RecovAlert])
+ );
+
+ prim_alert_sender #(
+ .AsyncOn(AlertAsyncOn[FatalAlert]),
+ .IsFatal(1)
+ ) u_prim_fatal_alert_sender (
+ .clk_i,
+ .rst_ni,
+ .alert_test_i(alert_test[FatalAlert]),
+ .alert_req_i(|reg2hw.fatal_alert),
+ .alert_ack_o(),
+ .alert_state_o(),
+ .alert_rx_i(alert_rx_i[FatalAlert]),
+ .alert_tx_o(alert_tx_o[FatalAlert])
+ );
+
+ ///////////////////////////
+ // wakeup generation
+ ///////////////////////////
+
+ // wakeups are synchronized separately from the normal event handling.
+ // The alert handling is not synchronized through these below because
+ // the ack latency would be very long for no apparent gain.
+
+ logic async_wake;
+ logic unstable_wake_req;
+
+ // async wake combines ast inputs as well as recoverable alerts.
+ // This is because it is possible for alert events to arrive "right"
+ // on the boundary of low power. In the event this happens, the
+ // original event is immediately 'acked', making it possible for the
+ // sync flops below to miss the event. By mixing in recov_alert,
+ // we guarantee that if the event is caught by the regfile, it can also
+ // be used to trigger wake from low power.
+ // Fatal alerts are not used here because they do not ever ack, meaning
+ // the originating event can never disappear.
+ assign async_wake = |async_alert_event_p |
+ ~&async_alert_event_n |
+ |reg2hw.recov_alert;
+
+ prim_flop_2sync #(
+ .Width(1),
+ .ResetValue('0)
+ ) u_wake_sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(async_wake),
+ .q_o(unstable_wake_req)
+ );
+
+ logic [2:0] wake_req_filter;
+ always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin
+ if (!rst_aon_ni) begin
+ wake_req_filter <= '0;
+ end else begin
+ wake_req_filter <= {wake_req_filter[1:0], unstable_wake_req};
+ end
+ end
+
+ // The filter is needed since the input is purely combinational
+ // among async events. The filter is thus used to ensure the
+ // wake indication is real and not a glitch.
+ always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin
+ if (!rst_aon_ni) begin
+ wkup_req_o <= '0;
+ end else begin
+ wkup_req_o <= |wake_req_filter;
+ end
+ end
+
///////////////////////////
// pinmux feedthrough to ast
///////////////////////////
diff --git a/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_pkg.sv b/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_pkg.sv
index 4c2c3e4..5aa8bf4 100644
--- a/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_pkg.sv
+++ b/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_pkg.sv
@@ -5,12 +5,12 @@
package sensor_ctrl_pkg;
- // Ack mode enumerations
- typedef enum logic [1:0] {
- ImmAck,
- SwAck,
- NoAck,
- InvalidAck // not a valid selection
- } ast_ack_mode_e;
+ // alert position
+ parameter int RecovAlert = 0;
+ parameter int FatalAlert = 1;
+
+ // Total events
+ parameter int TotalEvents = sensor_ctrl_reg_pkg::NumAlertEvents +
+ sensor_ctrl_reg_pkg::NumLocalEvents;
endpackage // sensor_ctrl_pkg
diff --git a/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_reg_pkg.sv b/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_reg_pkg.sv
index dc74247..25332bf 100644
--- a/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_reg_pkg.sv
@@ -7,7 +7,9 @@
package sensor_ctrl_reg_pkg;
// Param list
- parameter int NumAlerts = 13;
+ parameter int NumAlertEvents = 13;
+ parameter int NumLocalEvents = 1;
+ parameter int NumAlerts = 2;
parameter int NumIoRails = 2;
// Address widths within the block
@@ -21,74 +23,38 @@
struct packed {
logic q;
logic qe;
- } recov_as;
+ } recov_alert;
struct packed {
logic q;
logic qe;
- } recov_cg;
- struct packed {
- logic q;
- logic qe;
- } recov_gd;
- struct packed {
- logic q;
- logic qe;
- } recov_ts_hi;
- struct packed {
- logic q;
- logic qe;
- } recov_ts_lo;
- struct packed {
- logic q;
- logic qe;
- } recov_fla;
- struct packed {
- logic q;
- logic qe;
- } recov_otp;
- struct packed {
- logic q;
- logic qe;
- } recov_ot0;
- struct packed {
- logic q;
- logic qe;
- } recov_ot1;
- struct packed {
- logic q;
- logic qe;
- } recov_ot2;
- struct packed {
- logic q;
- logic qe;
- } recov_ot3;
- struct packed {
- logic q;
- logic qe;
- } recov_ot4;
- struct packed {
- logic q;
- logic qe;
- } recov_ot5;
+ } fatal_alert;
} sensor_ctrl_reg2hw_alert_test_reg_t;
typedef struct packed {
- logic [1:0] q;
- } sensor_ctrl_reg2hw_ack_mode_mreg_t;
-
- typedef struct packed {
logic q;
} sensor_ctrl_reg2hw_alert_trig_mreg_t;
typedef struct packed {
logic q;
- logic qe;
- } sensor_ctrl_reg2hw_alert_state_mreg_t;
+ } sensor_ctrl_reg2hw_fatal_alert_en_mreg_t;
+
+ typedef struct packed {
+ logic q;
+ } sensor_ctrl_reg2hw_recov_alert_mreg_t;
+
+ typedef struct packed {
+ logic q;
+ } sensor_ctrl_reg2hw_fatal_alert_mreg_t;
typedef struct packed {
logic d;
logic de;
- } sensor_ctrl_hw2reg_alert_state_mreg_t;
+ } sensor_ctrl_hw2reg_recov_alert_mreg_t;
+
+ typedef struct packed {
+ logic d;
+ logic de;
+ } sensor_ctrl_hw2reg_fatal_alert_mreg_t;
typedef struct packed {
struct packed {
@@ -103,60 +69,54 @@
// Register -> HW type
typedef struct packed {
- sensor_ctrl_reg2hw_alert_test_reg_t alert_test; // [90:65]
- sensor_ctrl_reg2hw_ack_mode_mreg_t [12:0] ack_mode; // [64:39]
- sensor_ctrl_reg2hw_alert_trig_mreg_t [12:0] alert_trig; // [38:26]
- sensor_ctrl_reg2hw_alert_state_mreg_t [12:0] alert_state; // [25:0]
+ sensor_ctrl_reg2hw_alert_test_reg_t alert_test; // [56:53]
+ sensor_ctrl_reg2hw_alert_trig_mreg_t [12:0] alert_trig; // [52:40]
+ sensor_ctrl_reg2hw_fatal_alert_en_mreg_t [12:0] fatal_alert_en; // [39:27]
+ sensor_ctrl_reg2hw_recov_alert_mreg_t [12:0] recov_alert; // [26:14]
+ sensor_ctrl_reg2hw_fatal_alert_mreg_t [13:0] fatal_alert; // [13:0]
} sensor_ctrl_reg2hw_t;
// HW -> register type
typedef struct packed {
- sensor_ctrl_hw2reg_alert_state_mreg_t [12:0] alert_state; // [30:5]
+ sensor_ctrl_hw2reg_recov_alert_mreg_t [12:0] recov_alert; // [58:33]
+ sensor_ctrl_hw2reg_fatal_alert_mreg_t [13:0] fatal_alert; // [32:5]
sensor_ctrl_hw2reg_status_reg_t status; // [4:0]
} sensor_ctrl_hw2reg_t;
// Register offsets
parameter logic [BlockAw-1:0] SENSOR_CTRL_ALERT_TEST_OFFSET = 5'h 0;
parameter logic [BlockAw-1:0] SENSOR_CTRL_CFG_REGWEN_OFFSET = 5'h 4;
- parameter logic [BlockAw-1:0] SENSOR_CTRL_ACK_MODE_OFFSET = 5'h 8;
- parameter logic [BlockAw-1:0] SENSOR_CTRL_ALERT_TRIG_OFFSET = 5'h c;
- parameter logic [BlockAw-1:0] SENSOR_CTRL_ALERT_STATE_OFFSET = 5'h 10;
- parameter logic [BlockAw-1:0] SENSOR_CTRL_STATUS_OFFSET = 5'h 14;
+ parameter logic [BlockAw-1:0] SENSOR_CTRL_ALERT_TRIG_OFFSET = 5'h 8;
+ parameter logic [BlockAw-1:0] SENSOR_CTRL_FATAL_ALERT_EN_OFFSET = 5'h c;
+ parameter logic [BlockAw-1:0] SENSOR_CTRL_RECOV_ALERT_OFFSET = 5'h 10;
+ parameter logic [BlockAw-1:0] SENSOR_CTRL_FATAL_ALERT_OFFSET = 5'h 14;
+ parameter logic [BlockAw-1:0] SENSOR_CTRL_STATUS_OFFSET = 5'h 18;
// Reset values for hwext registers and their fields
- parameter logic [12:0] SENSOR_CTRL_ALERT_TEST_RESVAL = 13'h 0;
- parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_AS_RESVAL = 1'h 0;
- parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_CG_RESVAL = 1'h 0;
- parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_GD_RESVAL = 1'h 0;
- parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_TS_HI_RESVAL = 1'h 0;
- parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_TS_LO_RESVAL = 1'h 0;
- parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_FLA_RESVAL = 1'h 0;
- parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_OTP_RESVAL = 1'h 0;
- parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_OT0_RESVAL = 1'h 0;
- parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_OT1_RESVAL = 1'h 0;
- parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_OT2_RESVAL = 1'h 0;
- parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_OT3_RESVAL = 1'h 0;
- parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_OT4_RESVAL = 1'h 0;
- parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_OT5_RESVAL = 1'h 0;
+ parameter logic [1:0] SENSOR_CTRL_ALERT_TEST_RESVAL = 2'h 0;
+ parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_ALERT_RESVAL = 1'h 0;
+ parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_FATAL_ALERT_RESVAL = 1'h 0;
// Register index
typedef enum int {
SENSOR_CTRL_ALERT_TEST,
SENSOR_CTRL_CFG_REGWEN,
- SENSOR_CTRL_ACK_MODE,
SENSOR_CTRL_ALERT_TRIG,
- SENSOR_CTRL_ALERT_STATE,
+ SENSOR_CTRL_FATAL_ALERT_EN,
+ SENSOR_CTRL_RECOV_ALERT,
+ SENSOR_CTRL_FATAL_ALERT,
SENSOR_CTRL_STATUS
} sensor_ctrl_id_e;
// Register width information to check illegal writes
- parameter logic [3:0] SENSOR_CTRL_PERMIT [6] = '{
- 4'b 0011, // index[0] SENSOR_CTRL_ALERT_TEST
+ parameter logic [3:0] SENSOR_CTRL_PERMIT [7] = '{
+ 4'b 0001, // index[0] SENSOR_CTRL_ALERT_TEST
4'b 0001, // index[1] SENSOR_CTRL_CFG_REGWEN
- 4'b 1111, // index[2] SENSOR_CTRL_ACK_MODE
- 4'b 0011, // index[3] SENSOR_CTRL_ALERT_TRIG
- 4'b 0011, // index[4] SENSOR_CTRL_ALERT_STATE
- 4'b 0001 // index[5] SENSOR_CTRL_STATUS
+ 4'b 0011, // index[2] SENSOR_CTRL_ALERT_TRIG
+ 4'b 0011, // index[3] SENSOR_CTRL_FATAL_ALERT_EN
+ 4'b 0011, // index[4] SENSOR_CTRL_RECOV_ALERT
+ 4'b 0011, // index[5] SENSOR_CTRL_FATAL_ALERT
+ 4'b 0001 // index[6] SENSOR_CTRL_STATUS
};
endpackage
diff --git a/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_reg_top.sv b/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_reg_top.sv
index e83ca30..265e9c9 100644
--- a/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_reg_top.sv
+++ b/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_reg_top.sv
@@ -109,49 +109,11 @@
// Format: <reg>_<field>_{wd|we|qs}
// or <reg>_{wd|we|qs} if field == 1 or 0
logic alert_test_we;
- logic alert_test_recov_as_wd;
- logic alert_test_recov_cg_wd;
- logic alert_test_recov_gd_wd;
- logic alert_test_recov_ts_hi_wd;
- logic alert_test_recov_ts_lo_wd;
- logic alert_test_recov_fla_wd;
- logic alert_test_recov_otp_wd;
- logic alert_test_recov_ot0_wd;
- logic alert_test_recov_ot1_wd;
- logic alert_test_recov_ot2_wd;
- logic alert_test_recov_ot3_wd;
- logic alert_test_recov_ot4_wd;
- logic alert_test_recov_ot5_wd;
+ logic alert_test_recov_alert_wd;
+ logic alert_test_fatal_alert_wd;
logic cfg_regwen_we;
logic cfg_regwen_qs;
logic cfg_regwen_wd;
- logic ack_mode_we;
- logic [1:0] ack_mode_val_0_qs;
- logic [1:0] ack_mode_val_0_wd;
- logic [1:0] ack_mode_val_1_qs;
- logic [1:0] ack_mode_val_1_wd;
- logic [1:0] ack_mode_val_2_qs;
- logic [1:0] ack_mode_val_2_wd;
- logic [1:0] ack_mode_val_3_qs;
- logic [1:0] ack_mode_val_3_wd;
- logic [1:0] ack_mode_val_4_qs;
- logic [1:0] ack_mode_val_4_wd;
- logic [1:0] ack_mode_val_5_qs;
- logic [1:0] ack_mode_val_5_wd;
- logic [1:0] ack_mode_val_6_qs;
- logic [1:0] ack_mode_val_6_wd;
- logic [1:0] ack_mode_val_7_qs;
- logic [1:0] ack_mode_val_7_wd;
- logic [1:0] ack_mode_val_8_qs;
- logic [1:0] ack_mode_val_8_wd;
- logic [1:0] ack_mode_val_9_qs;
- logic [1:0] ack_mode_val_9_wd;
- logic [1:0] ack_mode_val_10_qs;
- logic [1:0] ack_mode_val_10_wd;
- logic [1:0] ack_mode_val_11_qs;
- logic [1:0] ack_mode_val_11_wd;
- logic [1:0] ack_mode_val_12_qs;
- logic [1:0] ack_mode_val_12_wd;
logic alert_trig_we;
logic alert_trig_val_0_qs;
logic alert_trig_val_0_wd;
@@ -179,217 +141,104 @@
logic alert_trig_val_11_wd;
logic alert_trig_val_12_qs;
logic alert_trig_val_12_wd;
- logic alert_state_we;
- logic alert_state_val_0_qs;
- logic alert_state_val_0_wd;
- logic alert_state_val_1_qs;
- logic alert_state_val_1_wd;
- logic alert_state_val_2_qs;
- logic alert_state_val_2_wd;
- logic alert_state_val_3_qs;
- logic alert_state_val_3_wd;
- logic alert_state_val_4_qs;
- logic alert_state_val_4_wd;
- logic alert_state_val_5_qs;
- logic alert_state_val_5_wd;
- logic alert_state_val_6_qs;
- logic alert_state_val_6_wd;
- logic alert_state_val_7_qs;
- logic alert_state_val_7_wd;
- logic alert_state_val_8_qs;
- logic alert_state_val_8_wd;
- logic alert_state_val_9_qs;
- logic alert_state_val_9_wd;
- logic alert_state_val_10_qs;
- logic alert_state_val_10_wd;
- logic alert_state_val_11_qs;
- logic alert_state_val_11_wd;
- logic alert_state_val_12_qs;
- logic alert_state_val_12_wd;
+ logic fatal_alert_en_we;
+ logic fatal_alert_en_val_0_qs;
+ logic fatal_alert_en_val_0_wd;
+ logic fatal_alert_en_val_1_qs;
+ logic fatal_alert_en_val_1_wd;
+ logic fatal_alert_en_val_2_qs;
+ logic fatal_alert_en_val_2_wd;
+ logic fatal_alert_en_val_3_qs;
+ logic fatal_alert_en_val_3_wd;
+ logic fatal_alert_en_val_4_qs;
+ logic fatal_alert_en_val_4_wd;
+ logic fatal_alert_en_val_5_qs;
+ logic fatal_alert_en_val_5_wd;
+ logic fatal_alert_en_val_6_qs;
+ logic fatal_alert_en_val_6_wd;
+ logic fatal_alert_en_val_7_qs;
+ logic fatal_alert_en_val_7_wd;
+ logic fatal_alert_en_val_8_qs;
+ logic fatal_alert_en_val_8_wd;
+ logic fatal_alert_en_val_9_qs;
+ logic fatal_alert_en_val_9_wd;
+ logic fatal_alert_en_val_10_qs;
+ logic fatal_alert_en_val_10_wd;
+ logic fatal_alert_en_val_11_qs;
+ logic fatal_alert_en_val_11_wd;
+ logic fatal_alert_en_val_12_qs;
+ logic fatal_alert_en_val_12_wd;
+ logic recov_alert_we;
+ logic recov_alert_val_0_qs;
+ logic recov_alert_val_0_wd;
+ logic recov_alert_val_1_qs;
+ logic recov_alert_val_1_wd;
+ logic recov_alert_val_2_qs;
+ logic recov_alert_val_2_wd;
+ logic recov_alert_val_3_qs;
+ logic recov_alert_val_3_wd;
+ logic recov_alert_val_4_qs;
+ logic recov_alert_val_4_wd;
+ logic recov_alert_val_5_qs;
+ logic recov_alert_val_5_wd;
+ logic recov_alert_val_6_qs;
+ logic recov_alert_val_6_wd;
+ logic recov_alert_val_7_qs;
+ logic recov_alert_val_7_wd;
+ logic recov_alert_val_8_qs;
+ logic recov_alert_val_8_wd;
+ logic recov_alert_val_9_qs;
+ logic recov_alert_val_9_wd;
+ logic recov_alert_val_10_qs;
+ logic recov_alert_val_10_wd;
+ logic recov_alert_val_11_qs;
+ logic recov_alert_val_11_wd;
+ logic recov_alert_val_12_qs;
+ logic recov_alert_val_12_wd;
+ logic fatal_alert_val_0_qs;
+ logic fatal_alert_val_1_qs;
+ logic fatal_alert_val_2_qs;
+ logic fatal_alert_val_3_qs;
+ logic fatal_alert_val_4_qs;
+ logic fatal_alert_val_5_qs;
+ logic fatal_alert_val_6_qs;
+ logic fatal_alert_val_7_qs;
+ logic fatal_alert_val_8_qs;
+ logic fatal_alert_val_9_qs;
+ logic fatal_alert_val_10_qs;
+ logic fatal_alert_val_11_qs;
+ logic fatal_alert_val_12_qs;
+ logic fatal_alert_val_13_qs;
logic status_ast_init_done_qs;
logic [1:0] status_io_pok_qs;
// Register instances
// R[alert_test]: V(True)
- // F[recov_as]: 0:0
+ // F[recov_alert]: 0:0
prim_subreg_ext #(
.DW (1)
- ) u_alert_test_recov_as (
+ ) u_alert_test_recov_alert (
.re (1'b0),
.we (alert_test_we),
- .wd (alert_test_recov_as_wd),
+ .wd (alert_test_recov_alert_wd),
.d ('0),
.qre (),
- .qe (reg2hw.alert_test.recov_as.qe),
- .q (reg2hw.alert_test.recov_as.q),
+ .qe (reg2hw.alert_test.recov_alert.qe),
+ .q (reg2hw.alert_test.recov_alert.q),
.qs ()
);
- // F[recov_cg]: 1:1
+ // F[fatal_alert]: 1:1
prim_subreg_ext #(
.DW (1)
- ) u_alert_test_recov_cg (
+ ) u_alert_test_fatal_alert (
.re (1'b0),
.we (alert_test_we),
- .wd (alert_test_recov_cg_wd),
+ .wd (alert_test_fatal_alert_wd),
.d ('0),
.qre (),
- .qe (reg2hw.alert_test.recov_cg.qe),
- .q (reg2hw.alert_test.recov_cg.q),
- .qs ()
- );
-
- // F[recov_gd]: 2:2
- prim_subreg_ext #(
- .DW (1)
- ) u_alert_test_recov_gd (
- .re (1'b0),
- .we (alert_test_we),
- .wd (alert_test_recov_gd_wd),
- .d ('0),
- .qre (),
- .qe (reg2hw.alert_test.recov_gd.qe),
- .q (reg2hw.alert_test.recov_gd.q),
- .qs ()
- );
-
- // F[recov_ts_hi]: 3:3
- prim_subreg_ext #(
- .DW (1)
- ) u_alert_test_recov_ts_hi (
- .re (1'b0),
- .we (alert_test_we),
- .wd (alert_test_recov_ts_hi_wd),
- .d ('0),
- .qre (),
- .qe (reg2hw.alert_test.recov_ts_hi.qe),
- .q (reg2hw.alert_test.recov_ts_hi.q),
- .qs ()
- );
-
- // F[recov_ts_lo]: 4:4
- prim_subreg_ext #(
- .DW (1)
- ) u_alert_test_recov_ts_lo (
- .re (1'b0),
- .we (alert_test_we),
- .wd (alert_test_recov_ts_lo_wd),
- .d ('0),
- .qre (),
- .qe (reg2hw.alert_test.recov_ts_lo.qe),
- .q (reg2hw.alert_test.recov_ts_lo.q),
- .qs ()
- );
-
- // F[recov_fla]: 5:5
- prim_subreg_ext #(
- .DW (1)
- ) u_alert_test_recov_fla (
- .re (1'b0),
- .we (alert_test_we),
- .wd (alert_test_recov_fla_wd),
- .d ('0),
- .qre (),
- .qe (reg2hw.alert_test.recov_fla.qe),
- .q (reg2hw.alert_test.recov_fla.q),
- .qs ()
- );
-
- // F[recov_otp]: 6:6
- prim_subreg_ext #(
- .DW (1)
- ) u_alert_test_recov_otp (
- .re (1'b0),
- .we (alert_test_we),
- .wd (alert_test_recov_otp_wd),
- .d ('0),
- .qre (),
- .qe (reg2hw.alert_test.recov_otp.qe),
- .q (reg2hw.alert_test.recov_otp.q),
- .qs ()
- );
-
- // F[recov_ot0]: 7:7
- prim_subreg_ext #(
- .DW (1)
- ) u_alert_test_recov_ot0 (
- .re (1'b0),
- .we (alert_test_we),
- .wd (alert_test_recov_ot0_wd),
- .d ('0),
- .qre (),
- .qe (reg2hw.alert_test.recov_ot0.qe),
- .q (reg2hw.alert_test.recov_ot0.q),
- .qs ()
- );
-
- // F[recov_ot1]: 8:8
- prim_subreg_ext #(
- .DW (1)
- ) u_alert_test_recov_ot1 (
- .re (1'b0),
- .we (alert_test_we),
- .wd (alert_test_recov_ot1_wd),
- .d ('0),
- .qre (),
- .qe (reg2hw.alert_test.recov_ot1.qe),
- .q (reg2hw.alert_test.recov_ot1.q),
- .qs ()
- );
-
- // F[recov_ot2]: 9:9
- prim_subreg_ext #(
- .DW (1)
- ) u_alert_test_recov_ot2 (
- .re (1'b0),
- .we (alert_test_we),
- .wd (alert_test_recov_ot2_wd),
- .d ('0),
- .qre (),
- .qe (reg2hw.alert_test.recov_ot2.qe),
- .q (reg2hw.alert_test.recov_ot2.q),
- .qs ()
- );
-
- // F[recov_ot3]: 10:10
- prim_subreg_ext #(
- .DW (1)
- ) u_alert_test_recov_ot3 (
- .re (1'b0),
- .we (alert_test_we),
- .wd (alert_test_recov_ot3_wd),
- .d ('0),
- .qre (),
- .qe (reg2hw.alert_test.recov_ot3.qe),
- .q (reg2hw.alert_test.recov_ot3.q),
- .qs ()
- );
-
- // F[recov_ot4]: 11:11
- prim_subreg_ext #(
- .DW (1)
- ) u_alert_test_recov_ot4 (
- .re (1'b0),
- .we (alert_test_we),
- .wd (alert_test_recov_ot4_wd),
- .d ('0),
- .qre (),
- .qe (reg2hw.alert_test.recov_ot4.qe),
- .q (reg2hw.alert_test.recov_ot4.q),
- .qs ()
- );
-
- // F[recov_ot5]: 12:12
- prim_subreg_ext #(
- .DW (1)
- ) u_alert_test_recov_ot5 (
- .re (1'b0),
- .we (alert_test_we),
- .wd (alert_test_recov_ot5_wd),
- .d ('0),
- .qre (),
- .qe (reg2hw.alert_test.recov_ot5.qe),
- .q (reg2hw.alert_test.recov_ot5.q),
+ .qe (reg2hw.alert_test.fatal_alert.qe),
+ .q (reg2hw.alert_test.fatal_alert.q),
.qs ()
);
@@ -420,334 +269,6 @@
);
- // Subregister 0 of Multireg ack_mode
- // R[ack_mode]: V(False)
- // F[val_0]: 1:0
- prim_subreg #(
- .DW (2),
- .SwAccess(prim_subreg_pkg::SwAccessRW),
- .RESVAL (2'h0)
- ) u_ack_mode_val_0 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (ack_mode_we & cfg_regwen_qs),
- .wd (ack_mode_val_0_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.ack_mode[0].q),
-
- // to register interface (read)
- .qs (ack_mode_val_0_qs)
- );
-
- // F[val_1]: 3:2
- prim_subreg #(
- .DW (2),
- .SwAccess(prim_subreg_pkg::SwAccessRW),
- .RESVAL (2'h0)
- ) u_ack_mode_val_1 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (ack_mode_we & cfg_regwen_qs),
- .wd (ack_mode_val_1_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.ack_mode[1].q),
-
- // to register interface (read)
- .qs (ack_mode_val_1_qs)
- );
-
- // F[val_2]: 5:4
- prim_subreg #(
- .DW (2),
- .SwAccess(prim_subreg_pkg::SwAccessRW),
- .RESVAL (2'h0)
- ) u_ack_mode_val_2 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (ack_mode_we & cfg_regwen_qs),
- .wd (ack_mode_val_2_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.ack_mode[2].q),
-
- // to register interface (read)
- .qs (ack_mode_val_2_qs)
- );
-
- // F[val_3]: 7:6
- prim_subreg #(
- .DW (2),
- .SwAccess(prim_subreg_pkg::SwAccessRW),
- .RESVAL (2'h0)
- ) u_ack_mode_val_3 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (ack_mode_we & cfg_regwen_qs),
- .wd (ack_mode_val_3_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.ack_mode[3].q),
-
- // to register interface (read)
- .qs (ack_mode_val_3_qs)
- );
-
- // F[val_4]: 9:8
- prim_subreg #(
- .DW (2),
- .SwAccess(prim_subreg_pkg::SwAccessRW),
- .RESVAL (2'h0)
- ) u_ack_mode_val_4 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (ack_mode_we & cfg_regwen_qs),
- .wd (ack_mode_val_4_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.ack_mode[4].q),
-
- // to register interface (read)
- .qs (ack_mode_val_4_qs)
- );
-
- // F[val_5]: 11:10
- prim_subreg #(
- .DW (2),
- .SwAccess(prim_subreg_pkg::SwAccessRW),
- .RESVAL (2'h0)
- ) u_ack_mode_val_5 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (ack_mode_we & cfg_regwen_qs),
- .wd (ack_mode_val_5_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.ack_mode[5].q),
-
- // to register interface (read)
- .qs (ack_mode_val_5_qs)
- );
-
- // F[val_6]: 13:12
- prim_subreg #(
- .DW (2),
- .SwAccess(prim_subreg_pkg::SwAccessRW),
- .RESVAL (2'h0)
- ) u_ack_mode_val_6 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (ack_mode_we & cfg_regwen_qs),
- .wd (ack_mode_val_6_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.ack_mode[6].q),
-
- // to register interface (read)
- .qs (ack_mode_val_6_qs)
- );
-
- // F[val_7]: 15:14
- prim_subreg #(
- .DW (2),
- .SwAccess(prim_subreg_pkg::SwAccessRW),
- .RESVAL (2'h0)
- ) u_ack_mode_val_7 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (ack_mode_we & cfg_regwen_qs),
- .wd (ack_mode_val_7_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.ack_mode[7].q),
-
- // to register interface (read)
- .qs (ack_mode_val_7_qs)
- );
-
- // F[val_8]: 17:16
- prim_subreg #(
- .DW (2),
- .SwAccess(prim_subreg_pkg::SwAccessRW),
- .RESVAL (2'h0)
- ) u_ack_mode_val_8 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (ack_mode_we & cfg_regwen_qs),
- .wd (ack_mode_val_8_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.ack_mode[8].q),
-
- // to register interface (read)
- .qs (ack_mode_val_8_qs)
- );
-
- // F[val_9]: 19:18
- prim_subreg #(
- .DW (2),
- .SwAccess(prim_subreg_pkg::SwAccessRW),
- .RESVAL (2'h0)
- ) u_ack_mode_val_9 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (ack_mode_we & cfg_regwen_qs),
- .wd (ack_mode_val_9_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.ack_mode[9].q),
-
- // to register interface (read)
- .qs (ack_mode_val_9_qs)
- );
-
- // F[val_10]: 21:20
- prim_subreg #(
- .DW (2),
- .SwAccess(prim_subreg_pkg::SwAccessRW),
- .RESVAL (2'h0)
- ) u_ack_mode_val_10 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (ack_mode_we & cfg_regwen_qs),
- .wd (ack_mode_val_10_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.ack_mode[10].q),
-
- // to register interface (read)
- .qs (ack_mode_val_10_qs)
- );
-
- // F[val_11]: 23:22
- prim_subreg #(
- .DW (2),
- .SwAccess(prim_subreg_pkg::SwAccessRW),
- .RESVAL (2'h0)
- ) u_ack_mode_val_11 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (ack_mode_we & cfg_regwen_qs),
- .wd (ack_mode_val_11_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.ack_mode[11].q),
-
- // to register interface (read)
- .qs (ack_mode_val_11_qs)
- );
-
- // F[val_12]: 25:24
- prim_subreg #(
- .DW (2),
- .SwAccess(prim_subreg_pkg::SwAccessRW),
- .RESVAL (2'h0)
- ) u_ack_mode_val_12 (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (ack_mode_we & cfg_regwen_qs),
- .wd (ack_mode_val_12_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.ack_mode[12].q),
-
- // to register interface (read)
- .qs (ack_mode_val_12_qs)
- );
-
-
// Subregister 0 of Multireg alert_trig
// R[alert_trig]: V(False)
// F[val_0]: 0:0
@@ -1076,31 +597,359 @@
);
- // Subregister 0 of Multireg alert_state
- // R[alert_state]: V(False)
+ // Subregister 0 of Multireg fatal_alert_en
+ // R[fatal_alert_en]: V(False)
+ // F[val_0]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_en_val_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (fatal_alert_en_we & cfg_regwen_qs),
+ .wd (fatal_alert_en_val_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert_en[0].q),
+
+ // to register interface (read)
+ .qs (fatal_alert_en_val_0_qs)
+ );
+
+ // F[val_1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_en_val_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (fatal_alert_en_we & cfg_regwen_qs),
+ .wd (fatal_alert_en_val_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert_en[1].q),
+
+ // to register interface (read)
+ .qs (fatal_alert_en_val_1_qs)
+ );
+
+ // F[val_2]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_en_val_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (fatal_alert_en_we & cfg_regwen_qs),
+ .wd (fatal_alert_en_val_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert_en[2].q),
+
+ // to register interface (read)
+ .qs (fatal_alert_en_val_2_qs)
+ );
+
+ // F[val_3]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_en_val_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (fatal_alert_en_we & cfg_regwen_qs),
+ .wd (fatal_alert_en_val_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert_en[3].q),
+
+ // to register interface (read)
+ .qs (fatal_alert_en_val_3_qs)
+ );
+
+ // F[val_4]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_en_val_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (fatal_alert_en_we & cfg_regwen_qs),
+ .wd (fatal_alert_en_val_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert_en[4].q),
+
+ // to register interface (read)
+ .qs (fatal_alert_en_val_4_qs)
+ );
+
+ // F[val_5]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_en_val_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (fatal_alert_en_we & cfg_regwen_qs),
+ .wd (fatal_alert_en_val_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert_en[5].q),
+
+ // to register interface (read)
+ .qs (fatal_alert_en_val_5_qs)
+ );
+
+ // F[val_6]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_en_val_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (fatal_alert_en_we & cfg_regwen_qs),
+ .wd (fatal_alert_en_val_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert_en[6].q),
+
+ // to register interface (read)
+ .qs (fatal_alert_en_val_6_qs)
+ );
+
+ // F[val_7]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_en_val_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (fatal_alert_en_we & cfg_regwen_qs),
+ .wd (fatal_alert_en_val_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert_en[7].q),
+
+ // to register interface (read)
+ .qs (fatal_alert_en_val_7_qs)
+ );
+
+ // F[val_8]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_en_val_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (fatal_alert_en_we & cfg_regwen_qs),
+ .wd (fatal_alert_en_val_8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert_en[8].q),
+
+ // to register interface (read)
+ .qs (fatal_alert_en_val_8_qs)
+ );
+
+ // F[val_9]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_en_val_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (fatal_alert_en_we & cfg_regwen_qs),
+ .wd (fatal_alert_en_val_9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert_en[9].q),
+
+ // to register interface (read)
+ .qs (fatal_alert_en_val_9_qs)
+ );
+
+ // F[val_10]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_en_val_10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (fatal_alert_en_we & cfg_regwen_qs),
+ .wd (fatal_alert_en_val_10_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert_en[10].q),
+
+ // to register interface (read)
+ .qs (fatal_alert_en_val_10_qs)
+ );
+
+ // F[val_11]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_en_val_11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (fatal_alert_en_we & cfg_regwen_qs),
+ .wd (fatal_alert_en_val_11_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert_en[11].q),
+
+ // to register interface (read)
+ .qs (fatal_alert_en_val_11_qs)
+ );
+
+ // F[val_12]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_en_val_12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (fatal_alert_en_we & cfg_regwen_qs),
+ .wd (fatal_alert_en_val_12_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert_en[12].q),
+
+ // to register interface (read)
+ .qs (fatal_alert_en_val_12_qs)
+ );
+
+
+ // Subregister 0 of Multireg recov_alert
+ // R[recov_alert]: V(False)
// F[val_0]: 0:0
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
- ) u_alert_state_val_0 (
+ ) u_recov_alert_val_0 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
- .we (alert_state_we),
- .wd (alert_state_val_0_wd),
+ .we (recov_alert_we),
+ .wd (recov_alert_val_0_wd),
// from internal hardware
- .de (hw2reg.alert_state[0].de),
- .d (hw2reg.alert_state[0].d),
+ .de (hw2reg.recov_alert[0].de),
+ .d (hw2reg.recov_alert[0].d),
// to internal hardware
- .qe (reg2hw.alert_state[0].qe),
- .q (reg2hw.alert_state[0].q),
+ .qe (),
+ .q (reg2hw.recov_alert[0].q),
// to register interface (read)
- .qs (alert_state_val_0_qs)
+ .qs (recov_alert_val_0_qs)
);
// F[val_1]: 1:1
@@ -1108,24 +957,24 @@
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
- ) u_alert_state_val_1 (
+ ) u_recov_alert_val_1 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
- .we (alert_state_we),
- .wd (alert_state_val_1_wd),
+ .we (recov_alert_we),
+ .wd (recov_alert_val_1_wd),
// from internal hardware
- .de (hw2reg.alert_state[1].de),
- .d (hw2reg.alert_state[1].d),
+ .de (hw2reg.recov_alert[1].de),
+ .d (hw2reg.recov_alert[1].d),
// to internal hardware
- .qe (reg2hw.alert_state[1].qe),
- .q (reg2hw.alert_state[1].q),
+ .qe (),
+ .q (reg2hw.recov_alert[1].q),
// to register interface (read)
- .qs (alert_state_val_1_qs)
+ .qs (recov_alert_val_1_qs)
);
// F[val_2]: 2:2
@@ -1133,24 +982,24 @@
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
- ) u_alert_state_val_2 (
+ ) u_recov_alert_val_2 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
- .we (alert_state_we),
- .wd (alert_state_val_2_wd),
+ .we (recov_alert_we),
+ .wd (recov_alert_val_2_wd),
// from internal hardware
- .de (hw2reg.alert_state[2].de),
- .d (hw2reg.alert_state[2].d),
+ .de (hw2reg.recov_alert[2].de),
+ .d (hw2reg.recov_alert[2].d),
// to internal hardware
- .qe (reg2hw.alert_state[2].qe),
- .q (reg2hw.alert_state[2].q),
+ .qe (),
+ .q (reg2hw.recov_alert[2].q),
// to register interface (read)
- .qs (alert_state_val_2_qs)
+ .qs (recov_alert_val_2_qs)
);
// F[val_3]: 3:3
@@ -1158,24 +1007,24 @@
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
- ) u_alert_state_val_3 (
+ ) u_recov_alert_val_3 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
- .we (alert_state_we),
- .wd (alert_state_val_3_wd),
+ .we (recov_alert_we),
+ .wd (recov_alert_val_3_wd),
// from internal hardware
- .de (hw2reg.alert_state[3].de),
- .d (hw2reg.alert_state[3].d),
+ .de (hw2reg.recov_alert[3].de),
+ .d (hw2reg.recov_alert[3].d),
// to internal hardware
- .qe (reg2hw.alert_state[3].qe),
- .q (reg2hw.alert_state[3].q),
+ .qe (),
+ .q (reg2hw.recov_alert[3].q),
// to register interface (read)
- .qs (alert_state_val_3_qs)
+ .qs (recov_alert_val_3_qs)
);
// F[val_4]: 4:4
@@ -1183,24 +1032,24 @@
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
- ) u_alert_state_val_4 (
+ ) u_recov_alert_val_4 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
- .we (alert_state_we),
- .wd (alert_state_val_4_wd),
+ .we (recov_alert_we),
+ .wd (recov_alert_val_4_wd),
// from internal hardware
- .de (hw2reg.alert_state[4].de),
- .d (hw2reg.alert_state[4].d),
+ .de (hw2reg.recov_alert[4].de),
+ .d (hw2reg.recov_alert[4].d),
// to internal hardware
- .qe (reg2hw.alert_state[4].qe),
- .q (reg2hw.alert_state[4].q),
+ .qe (),
+ .q (reg2hw.recov_alert[4].q),
// to register interface (read)
- .qs (alert_state_val_4_qs)
+ .qs (recov_alert_val_4_qs)
);
// F[val_5]: 5:5
@@ -1208,24 +1057,24 @@
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
- ) u_alert_state_val_5 (
+ ) u_recov_alert_val_5 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
- .we (alert_state_we),
- .wd (alert_state_val_5_wd),
+ .we (recov_alert_we),
+ .wd (recov_alert_val_5_wd),
// from internal hardware
- .de (hw2reg.alert_state[5].de),
- .d (hw2reg.alert_state[5].d),
+ .de (hw2reg.recov_alert[5].de),
+ .d (hw2reg.recov_alert[5].d),
// to internal hardware
- .qe (reg2hw.alert_state[5].qe),
- .q (reg2hw.alert_state[5].q),
+ .qe (),
+ .q (reg2hw.recov_alert[5].q),
// to register interface (read)
- .qs (alert_state_val_5_qs)
+ .qs (recov_alert_val_5_qs)
);
// F[val_6]: 6:6
@@ -1233,24 +1082,24 @@
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
- ) u_alert_state_val_6 (
+ ) u_recov_alert_val_6 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
- .we (alert_state_we),
- .wd (alert_state_val_6_wd),
+ .we (recov_alert_we),
+ .wd (recov_alert_val_6_wd),
// from internal hardware
- .de (hw2reg.alert_state[6].de),
- .d (hw2reg.alert_state[6].d),
+ .de (hw2reg.recov_alert[6].de),
+ .d (hw2reg.recov_alert[6].d),
// to internal hardware
- .qe (reg2hw.alert_state[6].qe),
- .q (reg2hw.alert_state[6].q),
+ .qe (),
+ .q (reg2hw.recov_alert[6].q),
// to register interface (read)
- .qs (alert_state_val_6_qs)
+ .qs (recov_alert_val_6_qs)
);
// F[val_7]: 7:7
@@ -1258,24 +1107,24 @@
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
- ) u_alert_state_val_7 (
+ ) u_recov_alert_val_7 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
- .we (alert_state_we),
- .wd (alert_state_val_7_wd),
+ .we (recov_alert_we),
+ .wd (recov_alert_val_7_wd),
// from internal hardware
- .de (hw2reg.alert_state[7].de),
- .d (hw2reg.alert_state[7].d),
+ .de (hw2reg.recov_alert[7].de),
+ .d (hw2reg.recov_alert[7].d),
// to internal hardware
- .qe (reg2hw.alert_state[7].qe),
- .q (reg2hw.alert_state[7].q),
+ .qe (),
+ .q (reg2hw.recov_alert[7].q),
// to register interface (read)
- .qs (alert_state_val_7_qs)
+ .qs (recov_alert_val_7_qs)
);
// F[val_8]: 8:8
@@ -1283,24 +1132,24 @@
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
- ) u_alert_state_val_8 (
+ ) u_recov_alert_val_8 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
- .we (alert_state_we),
- .wd (alert_state_val_8_wd),
+ .we (recov_alert_we),
+ .wd (recov_alert_val_8_wd),
// from internal hardware
- .de (hw2reg.alert_state[8].de),
- .d (hw2reg.alert_state[8].d),
+ .de (hw2reg.recov_alert[8].de),
+ .d (hw2reg.recov_alert[8].d),
// to internal hardware
- .qe (reg2hw.alert_state[8].qe),
- .q (reg2hw.alert_state[8].q),
+ .qe (),
+ .q (reg2hw.recov_alert[8].q),
// to register interface (read)
- .qs (alert_state_val_8_qs)
+ .qs (recov_alert_val_8_qs)
);
// F[val_9]: 9:9
@@ -1308,24 +1157,24 @@
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
- ) u_alert_state_val_9 (
+ ) u_recov_alert_val_9 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
- .we (alert_state_we),
- .wd (alert_state_val_9_wd),
+ .we (recov_alert_we),
+ .wd (recov_alert_val_9_wd),
// from internal hardware
- .de (hw2reg.alert_state[9].de),
- .d (hw2reg.alert_state[9].d),
+ .de (hw2reg.recov_alert[9].de),
+ .d (hw2reg.recov_alert[9].d),
// to internal hardware
- .qe (reg2hw.alert_state[9].qe),
- .q (reg2hw.alert_state[9].q),
+ .qe (),
+ .q (reg2hw.recov_alert[9].q),
// to register interface (read)
- .qs (alert_state_val_9_qs)
+ .qs (recov_alert_val_9_qs)
);
// F[val_10]: 10:10
@@ -1333,24 +1182,24 @@
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
- ) u_alert_state_val_10 (
+ ) u_recov_alert_val_10 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
- .we (alert_state_we),
- .wd (alert_state_val_10_wd),
+ .we (recov_alert_we),
+ .wd (recov_alert_val_10_wd),
// from internal hardware
- .de (hw2reg.alert_state[10].de),
- .d (hw2reg.alert_state[10].d),
+ .de (hw2reg.recov_alert[10].de),
+ .d (hw2reg.recov_alert[10].d),
// to internal hardware
- .qe (reg2hw.alert_state[10].qe),
- .q (reg2hw.alert_state[10].q),
+ .qe (),
+ .q (reg2hw.recov_alert[10].q),
// to register interface (read)
- .qs (alert_state_val_10_qs)
+ .qs (recov_alert_val_10_qs)
);
// F[val_11]: 11:11
@@ -1358,24 +1207,24 @@
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
- ) u_alert_state_val_11 (
+ ) u_recov_alert_val_11 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
- .we (alert_state_we),
- .wd (alert_state_val_11_wd),
+ .we (recov_alert_we),
+ .wd (recov_alert_val_11_wd),
// from internal hardware
- .de (hw2reg.alert_state[11].de),
- .d (hw2reg.alert_state[11].d),
+ .de (hw2reg.recov_alert[11].de),
+ .d (hw2reg.recov_alert[11].d),
// to internal hardware
- .qe (reg2hw.alert_state[11].qe),
- .q (reg2hw.alert_state[11].q),
+ .qe (),
+ .q (reg2hw.recov_alert[11].q),
// to register interface (read)
- .qs (alert_state_val_11_qs)
+ .qs (recov_alert_val_11_qs)
);
// F[val_12]: 12:12
@@ -1383,24 +1232,377 @@
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
- ) u_alert_state_val_12 (
+ ) u_recov_alert_val_12 (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
- .we (alert_state_we),
- .wd (alert_state_val_12_wd),
+ .we (recov_alert_we),
+ .wd (recov_alert_val_12_wd),
// from internal hardware
- .de (hw2reg.alert_state[12].de),
- .d (hw2reg.alert_state[12].d),
+ .de (hw2reg.recov_alert[12].de),
+ .d (hw2reg.recov_alert[12].d),
// to internal hardware
- .qe (reg2hw.alert_state[12].qe),
- .q (reg2hw.alert_state[12].q),
+ .qe (),
+ .q (reg2hw.recov_alert[12].q),
// to register interface (read)
- .qs (alert_state_val_12_qs)
+ .qs (recov_alert_val_12_qs)
+ );
+
+
+ // Subregister 0 of Multireg fatal_alert
+ // R[fatal_alert]: V(False)
+ // F[val_0]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_val_0 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fatal_alert[0].de),
+ .d (hw2reg.fatal_alert[0].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert[0].q),
+
+ // to register interface (read)
+ .qs (fatal_alert_val_0_qs)
+ );
+
+ // F[val_1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_val_1 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fatal_alert[1].de),
+ .d (hw2reg.fatal_alert[1].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert[1].q),
+
+ // to register interface (read)
+ .qs (fatal_alert_val_1_qs)
+ );
+
+ // F[val_2]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_val_2 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fatal_alert[2].de),
+ .d (hw2reg.fatal_alert[2].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert[2].q),
+
+ // to register interface (read)
+ .qs (fatal_alert_val_2_qs)
+ );
+
+ // F[val_3]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_val_3 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fatal_alert[3].de),
+ .d (hw2reg.fatal_alert[3].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert[3].q),
+
+ // to register interface (read)
+ .qs (fatal_alert_val_3_qs)
+ );
+
+ // F[val_4]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_val_4 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fatal_alert[4].de),
+ .d (hw2reg.fatal_alert[4].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert[4].q),
+
+ // to register interface (read)
+ .qs (fatal_alert_val_4_qs)
+ );
+
+ // F[val_5]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_val_5 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fatal_alert[5].de),
+ .d (hw2reg.fatal_alert[5].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert[5].q),
+
+ // to register interface (read)
+ .qs (fatal_alert_val_5_qs)
+ );
+
+ // F[val_6]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_val_6 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fatal_alert[6].de),
+ .d (hw2reg.fatal_alert[6].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert[6].q),
+
+ // to register interface (read)
+ .qs (fatal_alert_val_6_qs)
+ );
+
+ // F[val_7]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_val_7 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fatal_alert[7].de),
+ .d (hw2reg.fatal_alert[7].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert[7].q),
+
+ // to register interface (read)
+ .qs (fatal_alert_val_7_qs)
+ );
+
+ // F[val_8]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_val_8 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fatal_alert[8].de),
+ .d (hw2reg.fatal_alert[8].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert[8].q),
+
+ // to register interface (read)
+ .qs (fatal_alert_val_8_qs)
+ );
+
+ // F[val_9]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_val_9 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fatal_alert[9].de),
+ .d (hw2reg.fatal_alert[9].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert[9].q),
+
+ // to register interface (read)
+ .qs (fatal_alert_val_9_qs)
+ );
+
+ // F[val_10]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_val_10 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fatal_alert[10].de),
+ .d (hw2reg.fatal_alert[10].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert[10].q),
+
+ // to register interface (read)
+ .qs (fatal_alert_val_10_qs)
+ );
+
+ // F[val_11]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_val_11 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fatal_alert[11].de),
+ .d (hw2reg.fatal_alert[11].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert[11].q),
+
+ // to register interface (read)
+ .qs (fatal_alert_val_11_qs)
+ );
+
+ // F[val_12]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_val_12 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fatal_alert[12].de),
+ .d (hw2reg.fatal_alert[12].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert[12].q),
+
+ // to register interface (read)
+ .qs (fatal_alert_val_12_qs)
+ );
+
+ // F[val_13]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRO),
+ .RESVAL (1'h0)
+ ) u_fatal_alert_val_13 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (1'b0),
+ .wd ('0),
+
+ // from internal hardware
+ .de (hw2reg.fatal_alert[13].de),
+ .d (hw2reg.fatal_alert[13].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.fatal_alert[13].q),
+
+ // to register interface (read)
+ .qs (fatal_alert_val_13_qs)
);
@@ -1457,15 +1659,16 @@
- logic [5:0] addr_hit;
+ logic [6:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[0] = (reg_addr == SENSOR_CTRL_ALERT_TEST_OFFSET);
addr_hit[1] = (reg_addr == SENSOR_CTRL_CFG_REGWEN_OFFSET);
- addr_hit[2] = (reg_addr == SENSOR_CTRL_ACK_MODE_OFFSET);
- addr_hit[3] = (reg_addr == SENSOR_CTRL_ALERT_TRIG_OFFSET);
- addr_hit[4] = (reg_addr == SENSOR_CTRL_ALERT_STATE_OFFSET);
- addr_hit[5] = (reg_addr == SENSOR_CTRL_STATUS_OFFSET);
+ addr_hit[2] = (reg_addr == SENSOR_CTRL_ALERT_TRIG_OFFSET);
+ addr_hit[3] = (reg_addr == SENSOR_CTRL_FATAL_ALERT_EN_OFFSET);
+ addr_hit[4] = (reg_addr == SENSOR_CTRL_RECOV_ALERT_OFFSET);
+ addr_hit[5] = (reg_addr == SENSOR_CTRL_FATAL_ALERT_OFFSET);
+ addr_hit[6] = (reg_addr == SENSOR_CTRL_STATUS_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -1478,66 +1681,18 @@
(addr_hit[2] & (|(SENSOR_CTRL_PERMIT[2] & ~reg_be))) |
(addr_hit[3] & (|(SENSOR_CTRL_PERMIT[3] & ~reg_be))) |
(addr_hit[4] & (|(SENSOR_CTRL_PERMIT[4] & ~reg_be))) |
- (addr_hit[5] & (|(SENSOR_CTRL_PERMIT[5] & ~reg_be)))));
+ (addr_hit[5] & (|(SENSOR_CTRL_PERMIT[5] & ~reg_be))) |
+ (addr_hit[6] & (|(SENSOR_CTRL_PERMIT[6] & ~reg_be)))));
end
assign alert_test_we = addr_hit[0] & reg_we & !reg_error;
- assign alert_test_recov_as_wd = reg_wdata[0];
+ assign alert_test_recov_alert_wd = reg_wdata[0];
- assign alert_test_recov_cg_wd = reg_wdata[1];
-
- assign alert_test_recov_gd_wd = reg_wdata[2];
-
- assign alert_test_recov_ts_hi_wd = reg_wdata[3];
-
- assign alert_test_recov_ts_lo_wd = reg_wdata[4];
-
- assign alert_test_recov_fla_wd = reg_wdata[5];
-
- assign alert_test_recov_otp_wd = reg_wdata[6];
-
- assign alert_test_recov_ot0_wd = reg_wdata[7];
-
- assign alert_test_recov_ot1_wd = reg_wdata[8];
-
- assign alert_test_recov_ot2_wd = reg_wdata[9];
-
- assign alert_test_recov_ot3_wd = reg_wdata[10];
-
- assign alert_test_recov_ot4_wd = reg_wdata[11];
-
- assign alert_test_recov_ot5_wd = reg_wdata[12];
+ assign alert_test_fatal_alert_wd = reg_wdata[1];
assign cfg_regwen_we = addr_hit[1] & reg_we & !reg_error;
assign cfg_regwen_wd = reg_wdata[0];
- assign ack_mode_we = addr_hit[2] & reg_we & !reg_error;
-
- assign ack_mode_val_0_wd = reg_wdata[1:0];
-
- assign ack_mode_val_1_wd = reg_wdata[3:2];
-
- assign ack_mode_val_2_wd = reg_wdata[5:4];
-
- assign ack_mode_val_3_wd = reg_wdata[7:6];
-
- assign ack_mode_val_4_wd = reg_wdata[9:8];
-
- assign ack_mode_val_5_wd = reg_wdata[11:10];
-
- assign ack_mode_val_6_wd = reg_wdata[13:12];
-
- assign ack_mode_val_7_wd = reg_wdata[15:14];
-
- assign ack_mode_val_8_wd = reg_wdata[17:16];
-
- assign ack_mode_val_9_wd = reg_wdata[19:18];
-
- assign ack_mode_val_10_wd = reg_wdata[21:20];
-
- assign ack_mode_val_11_wd = reg_wdata[23:22];
-
- assign ack_mode_val_12_wd = reg_wdata[25:24];
- assign alert_trig_we = addr_hit[3] & reg_we & !reg_error;
+ assign alert_trig_we = addr_hit[2] & reg_we & !reg_error;
assign alert_trig_val_0_wd = reg_wdata[0];
@@ -1564,33 +1719,60 @@
assign alert_trig_val_11_wd = reg_wdata[11];
assign alert_trig_val_12_wd = reg_wdata[12];
- assign alert_state_we = addr_hit[4] & reg_we & !reg_error;
+ assign fatal_alert_en_we = addr_hit[3] & reg_we & !reg_error;
- assign alert_state_val_0_wd = reg_wdata[0];
+ assign fatal_alert_en_val_0_wd = reg_wdata[0];
- assign alert_state_val_1_wd = reg_wdata[1];
+ assign fatal_alert_en_val_1_wd = reg_wdata[1];
- assign alert_state_val_2_wd = reg_wdata[2];
+ assign fatal_alert_en_val_2_wd = reg_wdata[2];
- assign alert_state_val_3_wd = reg_wdata[3];
+ assign fatal_alert_en_val_3_wd = reg_wdata[3];
- assign alert_state_val_4_wd = reg_wdata[4];
+ assign fatal_alert_en_val_4_wd = reg_wdata[4];
- assign alert_state_val_5_wd = reg_wdata[5];
+ assign fatal_alert_en_val_5_wd = reg_wdata[5];
- assign alert_state_val_6_wd = reg_wdata[6];
+ assign fatal_alert_en_val_6_wd = reg_wdata[6];
- assign alert_state_val_7_wd = reg_wdata[7];
+ assign fatal_alert_en_val_7_wd = reg_wdata[7];
- assign alert_state_val_8_wd = reg_wdata[8];
+ assign fatal_alert_en_val_8_wd = reg_wdata[8];
- assign alert_state_val_9_wd = reg_wdata[9];
+ assign fatal_alert_en_val_9_wd = reg_wdata[9];
- assign alert_state_val_10_wd = reg_wdata[10];
+ assign fatal_alert_en_val_10_wd = reg_wdata[10];
- assign alert_state_val_11_wd = reg_wdata[11];
+ assign fatal_alert_en_val_11_wd = reg_wdata[11];
- assign alert_state_val_12_wd = reg_wdata[12];
+ assign fatal_alert_en_val_12_wd = reg_wdata[12];
+ assign recov_alert_we = addr_hit[4] & reg_we & !reg_error;
+
+ assign recov_alert_val_0_wd = reg_wdata[0];
+
+ assign recov_alert_val_1_wd = reg_wdata[1];
+
+ assign recov_alert_val_2_wd = reg_wdata[2];
+
+ assign recov_alert_val_3_wd = reg_wdata[3];
+
+ assign recov_alert_val_4_wd = reg_wdata[4];
+
+ assign recov_alert_val_5_wd = reg_wdata[5];
+
+ assign recov_alert_val_6_wd = reg_wdata[6];
+
+ assign recov_alert_val_7_wd = reg_wdata[7];
+
+ assign recov_alert_val_8_wd = reg_wdata[8];
+
+ assign recov_alert_val_9_wd = reg_wdata[9];
+
+ assign recov_alert_val_10_wd = reg_wdata[10];
+
+ assign recov_alert_val_11_wd = reg_wdata[11];
+
+ assign recov_alert_val_12_wd = reg_wdata[12];
// Read data return
always_comb begin
@@ -1599,17 +1781,6 @@
addr_hit[0]: begin
reg_rdata_next[0] = '0;
reg_rdata_next[1] = '0;
- reg_rdata_next[2] = '0;
- reg_rdata_next[3] = '0;
- reg_rdata_next[4] = '0;
- reg_rdata_next[5] = '0;
- reg_rdata_next[6] = '0;
- reg_rdata_next[7] = '0;
- reg_rdata_next[8] = '0;
- reg_rdata_next[9] = '0;
- reg_rdata_next[10] = '0;
- reg_rdata_next[11] = '0;
- reg_rdata_next[12] = '0;
end
addr_hit[1]: begin
@@ -1617,22 +1788,6 @@
end
addr_hit[2]: begin
- reg_rdata_next[1:0] = ack_mode_val_0_qs;
- reg_rdata_next[3:2] = ack_mode_val_1_qs;
- reg_rdata_next[5:4] = ack_mode_val_2_qs;
- reg_rdata_next[7:6] = ack_mode_val_3_qs;
- reg_rdata_next[9:8] = ack_mode_val_4_qs;
- reg_rdata_next[11:10] = ack_mode_val_5_qs;
- reg_rdata_next[13:12] = ack_mode_val_6_qs;
- reg_rdata_next[15:14] = ack_mode_val_7_qs;
- reg_rdata_next[17:16] = ack_mode_val_8_qs;
- reg_rdata_next[19:18] = ack_mode_val_9_qs;
- reg_rdata_next[21:20] = ack_mode_val_10_qs;
- reg_rdata_next[23:22] = ack_mode_val_11_qs;
- reg_rdata_next[25:24] = ack_mode_val_12_qs;
- end
-
- addr_hit[3]: begin
reg_rdata_next[0] = alert_trig_val_0_qs;
reg_rdata_next[1] = alert_trig_val_1_qs;
reg_rdata_next[2] = alert_trig_val_2_qs;
@@ -1648,23 +1803,56 @@
reg_rdata_next[12] = alert_trig_val_12_qs;
end
+ addr_hit[3]: begin
+ reg_rdata_next[0] = fatal_alert_en_val_0_qs;
+ reg_rdata_next[1] = fatal_alert_en_val_1_qs;
+ reg_rdata_next[2] = fatal_alert_en_val_2_qs;
+ reg_rdata_next[3] = fatal_alert_en_val_3_qs;
+ reg_rdata_next[4] = fatal_alert_en_val_4_qs;
+ reg_rdata_next[5] = fatal_alert_en_val_5_qs;
+ reg_rdata_next[6] = fatal_alert_en_val_6_qs;
+ reg_rdata_next[7] = fatal_alert_en_val_7_qs;
+ reg_rdata_next[8] = fatal_alert_en_val_8_qs;
+ reg_rdata_next[9] = fatal_alert_en_val_9_qs;
+ reg_rdata_next[10] = fatal_alert_en_val_10_qs;
+ reg_rdata_next[11] = fatal_alert_en_val_11_qs;
+ reg_rdata_next[12] = fatal_alert_en_val_12_qs;
+ end
+
addr_hit[4]: begin
- reg_rdata_next[0] = alert_state_val_0_qs;
- reg_rdata_next[1] = alert_state_val_1_qs;
- reg_rdata_next[2] = alert_state_val_2_qs;
- reg_rdata_next[3] = alert_state_val_3_qs;
- reg_rdata_next[4] = alert_state_val_4_qs;
- reg_rdata_next[5] = alert_state_val_5_qs;
- reg_rdata_next[6] = alert_state_val_6_qs;
- reg_rdata_next[7] = alert_state_val_7_qs;
- reg_rdata_next[8] = alert_state_val_8_qs;
- reg_rdata_next[9] = alert_state_val_9_qs;
- reg_rdata_next[10] = alert_state_val_10_qs;
- reg_rdata_next[11] = alert_state_val_11_qs;
- reg_rdata_next[12] = alert_state_val_12_qs;
+ reg_rdata_next[0] = recov_alert_val_0_qs;
+ reg_rdata_next[1] = recov_alert_val_1_qs;
+ reg_rdata_next[2] = recov_alert_val_2_qs;
+ reg_rdata_next[3] = recov_alert_val_3_qs;
+ reg_rdata_next[4] = recov_alert_val_4_qs;
+ reg_rdata_next[5] = recov_alert_val_5_qs;
+ reg_rdata_next[6] = recov_alert_val_6_qs;
+ reg_rdata_next[7] = recov_alert_val_7_qs;
+ reg_rdata_next[8] = recov_alert_val_8_qs;
+ reg_rdata_next[9] = recov_alert_val_9_qs;
+ reg_rdata_next[10] = recov_alert_val_10_qs;
+ reg_rdata_next[11] = recov_alert_val_11_qs;
+ reg_rdata_next[12] = recov_alert_val_12_qs;
end
addr_hit[5]: begin
+ reg_rdata_next[0] = fatal_alert_val_0_qs;
+ reg_rdata_next[1] = fatal_alert_val_1_qs;
+ reg_rdata_next[2] = fatal_alert_val_2_qs;
+ reg_rdata_next[3] = fatal_alert_val_3_qs;
+ reg_rdata_next[4] = fatal_alert_val_4_qs;
+ reg_rdata_next[5] = fatal_alert_val_5_qs;
+ reg_rdata_next[6] = fatal_alert_val_6_qs;
+ reg_rdata_next[7] = fatal_alert_val_7_qs;
+ reg_rdata_next[8] = fatal_alert_val_8_qs;
+ reg_rdata_next[9] = fatal_alert_val_9_qs;
+ reg_rdata_next[10] = fatal_alert_val_10_qs;
+ reg_rdata_next[11] = fatal_alert_val_11_qs;
+ reg_rdata_next[12] = fatal_alert_val_12_qs;
+ reg_rdata_next[13] = fatal_alert_val_13_qs;
+ end
+
+ addr_hit[6]: begin
reg_rdata_next[0] = status_ast_init_done_qs;
reg_rdata_next[2:1] = status_io_pok_qs;
end
diff --git a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
index 8501309..35c5c7a 100644
--- a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
+++ b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
@@ -278,15 +278,6 @@
base_addr: "0x40470000",
attr: "templated",
},
- { name: "sensor_ctrl_aon",
- type: "sensor_ctrl",
- clock_srcs: {clk_i: "io_div4"},
- clock_group: "secure",
- reset_connections: {rst_ni: "sys_io_div4"},
- domain: ["Aon"],
- base_addr: "0x40490000",
- attr: "reggen_top",
- },
{ name: "sram_ctrl_ret_aon",
type: "sram_ctrl",
clock_srcs: {clk_i: "io_div4", clk_otp_i: "io_div4"},
@@ -632,10 +623,6 @@
# 'otp_ctrl.otp_ast_pwr_seq_h' : '',
# 'otp_ctrl.otp_alert' : 'otp_alert',
'rstmgr_aon.por_n' : 'por_n'
- 'sensor_ctrl_aon.ast_alert' : 'sensor_ctrl_ast_alert',
- 'sensor_ctrl_aon.ast_status' : 'sensor_ctrl_ast_status',
- 'sensor_ctrl_aon.ast2pinmux' : '',
- # 'sensor_ctrl_aon.ast_init_done': 'ast_init_done',
'usbdev.usb_ref_val' : '',
'usbdev.usb_ref_pulse' : '',
},
@@ -834,7 +821,6 @@
{ instance: "gpio", port: '', connection: 'muxed' , pad: '' , desc: ''},
{ instance: "uart0", port: '', connection: 'muxed' , pad: '' , desc: ''},
{ instance: "flash_ctrl", port: '', connection: 'muxed' , pad: '' , desc: ''},
- { instance: "sensor_ctrl_aon", port: '', connection: 'muxed' , pad: '' , desc: ''},
],
// Number of wakeup detectors to instantiate, and bitwidth for the wakeup counters.
diff --git a/hw/top_englishbreakfast/data/xbar_peri.hjson b/hw/top_englishbreakfast/data/xbar_peri.hjson
index e8f96f9..4cc54e4 100644
--- a/hw/top_englishbreakfast/data/xbar_peri.hjson
+++ b/hw/top_englishbreakfast/data/xbar_peri.hjson
@@ -81,12 +81,6 @@
reset: "rst_peri_ni",
pipeline: "false"
},
- { name: "sensor_ctrl_aon",
- type: "device",
- clock: "clk_peri_i",
- reset: "rst_peri_ni",
- pipeline: "false",
- },
{ name: "sram_ctrl_ret_aon.regs",
type: "device",
clock: "clk_peri_i",
@@ -105,7 +99,7 @@
"uart0",
"gpio", "spi_device", "spi_host0", "rv_timer", "usbdev",
"pwrmgr_aon", "rstmgr_aon", "clkmgr_aon", "pinmux_aon",
- "lc_ctrl", "sensor_ctrl_aon",
+ "lc_ctrl",
"sram_ctrl_ret_aon.ram", "sram_ctrl_ret_aon.regs",
],
},
diff --git a/hw/top_englishbreakfast/rtl/chip_englishbreakfast_verilator.sv b/hw/top_englishbreakfast/rtl/chip_englishbreakfast_verilator.sv
index 8f3e8a1..c5043a3 100644
--- a/hw/top_englishbreakfast/rtl/chip_englishbreakfast_verilator.sv
+++ b/hw/top_englishbreakfast/rtl/chip_englishbreakfast_verilator.sv
@@ -170,9 +170,6 @@
.clk_main_jitter_en_o ( ),
.pwrmgr_ast_req_o ( ),
.pwrmgr_ast_rsp_i ( ast_base_pwr ),
- .sensor_ctrl_ast_alert_req_i ( ast_base_alerts ),
- .sensor_ctrl_ast_alert_rsp_o ( ),
- .sensor_ctrl_ast_status_i ( ast_base_status ),
.usbdev_usb_ref_val_o ( ),
.usbdev_usb_ref_pulse_o ( ),
.ast_edn_req_i ( '0 ),
diff --git a/sw/device/lib/dif/dif_alert_handler_unittest.cc b/sw/device/lib/dif/dif_alert_handler_unittest.cc
index b2a5f4b..0578760 100644
--- a/sw/device/lib/dif/dif_alert_handler_unittest.cc
+++ b/sw/device/lib/dif/dif_alert_handler_unittest.cc
@@ -59,7 +59,7 @@
}
INSTANTIATE_TEST_SUITE_P(InitTestSignalCounts, InitTest,
- testing::Values(1, 2, 12, 16, 24, 32, 64,
+ testing::Values(1, 2, 12, 16, 24, 32, 48,
ALERT_HANDLER_PARAM_N_ALERTS));
class ConfigTest : public AlertTest {
diff --git a/util/topgen/templates/chiplevel.sv.tpl b/util/topgen/templates/chiplevel.sv.tpl
index 998091f..bf8453e 100644
--- a/util/topgen/templates/chiplevel.sv.tpl
+++ b/util/topgen/templates/chiplevel.sv.tpl
@@ -1099,9 +1099,6 @@
.rsts_ast_o ( ),
.pwrmgr_ast_req_o ( ),
.pwrmgr_ast_rsp_i ( ast_base_pwr ),
- .sensor_ctrl_ast_alert_req_i ( ast_base_alerts ),
- .sensor_ctrl_ast_alert_rsp_o ( ),
- .sensor_ctrl_ast_status_i ( ast_base_status ),
.usbdev_usb_ref_val_o ( ),
.usbdev_usb_ref_pulse_o ( ),
.ast_edn_req_i ( '0 ),
@@ -1118,6 +1115,9 @@
.otp_ctrl_otp_ast_pwr_seq_o ( ),
.otp_ctrl_otp_ast_pwr_seq_h_i ( '0 ),
.otp_alert_o ( ),
+ .sensor_ctrl_ast_alert_req_i ( ast_base_alerts ),
+ .sensor_ctrl_ast_alert_rsp_o ( ),
+ .sensor_ctrl_ast_status_i ( ast_base_status ),
.es_rng_req_o ( ),
.es_rng_rsp_i ( '0 ),
.es_rng_fips_o ( ),
