commit 444055d8610c376240104b9f2acc397c4152aef3
author Timothy Chen <timothytim@google.com> Thu Oct 17 12:22:12 2019 -0700
committer tjaychen <timothytim@google.com> Thu Oct 17 14:08:37 2019 -0700
tree 11c18748daf70f3a240c82d1c2994faef1946cec
parent 698d6769df07033d919586d3ceefe940612f8cd4

[fpga] Minor fixes to splicing

- update ROM search path
- update script to automatically move spliced bitfile

hw/top_earlgrey/data/placement.xdc

diff --git a/hw/top_earlgrey/data/placement.xdc b/hw/top_earlgrey/data/placement.xdc
index a9e7eb8..ca97e59 100644
--- a/hw/top_earlgrey/data/placement.xdc
+++ b/hw/top_earlgrey/data/placement.xdc
@@ -1,2 +1,2 @@
-set_property LOC RAMB36_X4Y18 [get_cells -hierarchical -filter { NAME =~  "*rom_rom*mem_reg_0" && PRIMITIVE_TYPE =~ BMEM.*.* }]
-set_property LOC RAMB36_X4Y19 [get_cells -hierarchical -filter { NAME =~  "*rom_rom*mem_reg_1" && PRIMITIVE_TYPE =~ BMEM.*.* }]
+set_property LOC RAMB36_X4Y18 [get_cells -hierarchical -filter { NAME =~  "*rom_rom*dout_o_reg_0" && PRIMITIVE_TYPE =~ BMEM.*.* }]
+set_property LOC RAMB36_X4Y19 [get_cells -hierarchical -filter { NAME =~  "*rom_rom*dout_o_reg_1" && PRIMITIVE_TYPE =~ BMEM.*.* }]

util/fpga/splice_nexysvideo.sh

diff --git a/util/fpga/splice_nexysvideo.sh b/util/fpga/splice_nexysvideo.sh
index 88e1396..062223d 100755
--- a/util/fpga/splice_nexysvideo.sh
+++ b/util/fpga/splice_nexysvideo.sh
@@ -30,3 +30,6 @@
   --data ${TARGET_PREFIX}.mem \
   --bit "${FPGA_BUILD_DIR}/${FPGA_BIT_NAME}.bit"  --proc dummy \
   --out "${FPGA_BUILD_DIR}/${FPGA_BIT_NAME}.splice.bit"
+
+mv ${FPGA_BUILD_DIR}/${FPGA_BIT_NAME}.bit ${FPGA_BUILD_DIR}/${FPGA_BIT_NAME}.bit.orig
+mv ${FPGA_BUILD_DIR}/${FPGA_BIT_NAME}.splice.bit ${FPGA_BUILD_DIR}/${FPGA_BIT_NAME}.bit