[prim_fifo_sync] Add synchronous clear signal to the FIFO primitive
This adds a synchronous clr signal to the synchronous FIFO primitive
which synchronously resets the read and write pointers to zero if
asserted. This has been used to replace some of the gated asynchronous
resets in the design.
diff --git a/hw/ip/hmac/rtl/hmac.sv b/hw/ip/hmac/rtl/hmac.sv
index ade45a3..cc5fbf5 100644
--- a/hw/ip/hmac/rtl/hmac.sv
+++ b/hw/ip/hmac/rtl/hmac.sv
@@ -194,6 +194,7 @@
) u_msg_fifo (
.clk_i,
.rst_ni,
+ .clr_i (1'b0),
.wvalid (fifo_wvalid & sha_en),
.wready (fifo_wready),
diff --git a/hw/ip/i2c/rtl/i2c_core.sv b/hw/ip/i2c/rtl/i2c_core.sv
index 48f307c..8de8be4 100644
--- a/hw/ip/i2c/rtl/i2c_core.sv
+++ b/hw/ip/i2c/rtl/i2c_core.sv
@@ -59,7 +59,6 @@
logic override;
- logic fmt_fifo_rst_n;
logic fmt_fifo_wvalid;
logic fmt_fifo_wready;
logic [12:0] fmt_fifo_wdata;
@@ -77,7 +76,6 @@
logic [1:0] i2c_fifo_fmtilvl;
logic [2:0] i2c_fifo_rxilvl;
- logic rx_fifo_rst_n;
logic rx_fifo_wvalid;
logic rx_fifo_wready;
logic [7:0] rx_fifo_wdata;
@@ -180,15 +178,15 @@
assign fmt_flag_read_bytes = fmt_fifo_rdata[11];
assign fmt_flag_nak_ok = fmt_fifo_rdata[12];
- assign fmt_fifo_rst_n = scanmode_i ? rst_ni : (rst_ni & ~reg2hw.fifo_ctrl.fmtrst.q);
-
prim_fifo_sync #(
.Width(13),
.Pass(1'b1),
.Depth(32)
) u_i2c_fmtfifo (
.clk_i,
- .rst_ni(fmt_fifo_rst_n),
+ .rst_ni,
+ // TODO: check whether qe could be used as clear strobe
+ .clr_i (reg2hw.fifo_ctrl.fmtrst.q),
.wvalid(fmt_fifo_wvalid),
.wready(fmt_fifo_wready),
.wdata(fmt_fifo_wdata),
@@ -199,7 +197,6 @@
);
assign rx_fifo_rready = reg2hw.rdata.re;
- assign rx_fifo_rst_n = scanmode_i ? rst_ni : (rst_ni & ~reg2hw.fifo_ctrl.rxrst.q);
prim_fifo_sync #(
.Width(8),
@@ -207,7 +204,9 @@
.Depth(32)
) u_i2c_rxfifo (
.clk_i,
- .rst_ni(rx_fifo_rst_n),
+ .rst_ni,
+ // TODO: check whether qe could be used as clear strobe
+ .clr_i(reg2hw.fifo_ctrl.rxrst.q),
.wvalid(rx_fifo_wvalid),
.wready(rx_fifo_wready),
.wdata(rx_fifo_wdata),
diff --git a/hw/ip/prim/rtl/prim_fifo_sync.sv b/hw/ip/prim/rtl/prim_fifo_sync.sv
index 8bd356b..d066eda 100644
--- a/hw/ip/prim/rtl/prim_fifo_sync.sv
+++ b/hw/ip/prim/rtl/prim_fifo_sync.sv
@@ -13,6 +13,8 @@
) (
input clk_i,
input rst_ni,
+ // synchronous clear / flush port
+ input clr_i,
// write port
input wvalid,
output wready,
@@ -70,25 +72,31 @@
assign wready = ~full;
assign rvalid = ~empty;
- always_ff @(posedge clk_i or negedge rst_ni)
+ always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
fifo_wptr <= {(PTR_WIDTH){1'b0}};
+ end else if (clr_i) begin
+ fifo_wptr <= {(PTR_WIDTH){1'b0}};
end else if (fifo_incr_wptr) begin
if (fifo_wptr[PTR_WIDTH-2:0] == (Depth-1)) begin
fifo_wptr <= {~fifo_wptr[PTR_WIDTH-1],{(PTR_WIDTH-1){1'b0}}};
end else begin
fifo_wptr <= fifo_wptr + {{(PTR_WIDTH-1){1'b0}},1'b1};
+ end
end
end
- always_ff @(posedge clk_i or negedge rst_ni)
+ always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
fifo_rptr <= {(PTR_WIDTH){1'b0}};
+ end else if (clr_i) begin
+ fifo_rptr <= {(PTR_WIDTH){1'b0}};
end else if (fifo_incr_rptr) begin
if (fifo_rptr[PTR_WIDTH-2:0] == (Depth-1)) begin
fifo_rptr <= {~fifo_rptr[PTR_WIDTH-1],{(PTR_WIDTH-1){1'b0}}};
end else begin
fifo_rptr <= fifo_rptr + {{(PTR_WIDTH-1){1'b0}},1'b1};
+ end
end
end
diff --git a/hw/ip/prim/rtl/prim_sram_arbiter.sv b/hw/ip/prim/rtl/prim_sram_arbiter.sv
index a60d81d..1dac50d 100644
--- a/hw/ip/prim/rtl/prim_sram_arbiter.sv
+++ b/hw/ip/prim/rtl/prim_sram_arbiter.sv
@@ -84,6 +84,7 @@
) u_req_fifo (
.clk_i,
.rst_ni,
+ .clr_i (1'b0),
.wvalid (sram_req && !sram_write), // Push only for read
.wready (), // TODO: Generate Error
.wdata (gnt),
diff --git a/hw/ip/tlul/rtl/tlul_adapter_sram.sv b/hw/ip/tlul/rtl/tlul_adapter_sram.sv
index 0d76cea..69d0a73 100644
--- a/hw/ip/tlul/rtl/tlul_adapter_sram.sv
+++ b/hw/ip/tlul/rtl/tlul_adapter_sram.sv
@@ -225,6 +225,7 @@
) u_reqfifo (
.clk_i,
.rst_ni,
+ .clr_i (1'b0),
.wvalid (reqfifo_wvalid),
.wready (reqfifo_wready),
.wdata (reqfifo_wdata),
@@ -247,6 +248,7 @@
) u_rspfifo (
.clk_i,
.rst_ni,
+ .clr_i (1'b0),
.wvalid (rspfifo_wvalid),
.wready (rspfifo_wready),
.wdata (rspfifo_wdata),
diff --git a/hw/ip/tlul/rtl/tlul_fifo_sync.sv b/hw/ip/tlul/rtl/tlul_fifo_sync.sv
index 4d9a4bc..a3b1b58 100644
--- a/hw/ip/tlul/rtl/tlul_fifo_sync.sv
+++ b/hw/ip/tlul/rtl/tlul_fifo_sync.sv
@@ -32,6 +32,7 @@
prim_fifo_sync #(.Width(REQFIFO_WIDTH), .Pass(ReqPass), .Depth(ReqDepth)) reqfifo (
.clk_i,
.rst_ni,
+ .clr_i (1'b0 ),
.wvalid (tl_h_i.a_valid),
.wready (tl_h_o.a_ready),
.wdata ({tl_h_i.a_opcode ,
@@ -63,6 +64,7 @@
prim_fifo_sync #(.Width(RSPFIFO_WIDTH), .Pass(RspPass), .Depth(RspDepth)) rspfifo (
.clk_i,
.rst_ni,
+ .clr_i (1'b0 ),
.wvalid (tl_d_i.d_valid),
.wready (tl_d_o.d_ready),
.wdata ({tl_d_i.d_opcode,
diff --git a/hw/ip/uart/rtl/uart_core.sv b/hw/ip/uart/rtl/uart_core.sv
index 62e14b9..e77a4c4 100644
--- a/hw/ip/uart/rtl/uart_core.sv
+++ b/hw/ip/uart/rtl/uart_core.sv
@@ -31,7 +31,6 @@
logic [15:0] rx_val_q;
logic [7:0] uart_rdata;
logic tick_baud_x16, rx_tick_baud;
- logic tx_fifo_rst_n, rx_fifo_rst_n;
logic [5:0] tx_fifo_depth, rx_fifo_depth;
logic [5:0] rx_fifo_depth_prev_q;
logic [23:0] rx_timeout_count_d, rx_timeout_count_q, uart_rxto_val;
@@ -166,7 +165,6 @@
// TX Logic
assign tx_fifo_rready = tx_uart_idle & tx_fifo_rvalid & tx_enable;
- assign tx_fifo_rst_n = scanmode_i ? rst_ni : (rst_ni & ~uart_fifo_txrst);
prim_fifo_sync #(
.Width(8),
@@ -174,7 +172,8 @@
.Depth(32)
) u_uart_txfifo (
.clk_i,
- .rst_ni (tx_fifo_rst_n),
+ .rst_ni,
+ .clr_i (uart_fifo_txrst),
.wvalid (reg2hw.wdata.qe),
.wready (tx_fifo_wready),
.wdata (reg2hw.wdata.q),
@@ -264,15 +263,15 @@
);
assign rx_fifo_wvalid = rx_valid & ~event_rx_frame_err & ~event_rx_parity_err;
- assign rx_fifo_rst_n = scanmode_i ? rst_ni : (rst_ni & ~uart_fifo_rxrst);
prim_fifo_sync #(
.Width (8),
.Pass (1'b0),
.Depth (32)
) u_uart_rxfifo (
- .clk_i (clk_i),
- .rst_ni (rx_fifo_rst_n),
+ .clk_i,
+ .rst_ni,
+ .clr_i (uart_fifo_rxrst),
.wvalid (rx_fifo_wvalid),
.wready (rx_fifo_wready),
.wdata (rx_fifo_data),
