[fpv] Update FPV file naming
This PR updates the naming post fix from _fpv to _tb, according to the suggestion from PR #8616.
Signed-off-by: Cindy Chen <chencindy@opentitan.org>
diff --git a/hw/ip/pinmux/fpv/pinmux_fpv.core b/hw/ip/pinmux/fpv/pinmux_fpv.core
index 7da070a..26ea3c1 100644
--- a/hw/ip/pinmux/fpv/pinmux_fpv.core
+++ b/hw/ip/pinmux/fpv/pinmux_fpv.core
@@ -14,7 +14,7 @@
files:
- vip/pinmux_assert_fpv.sv
- tb/pinmux_bind_fpv.sv
- - tb/pinmux_fpv.sv
+ - tb/pinmux_tb.sv
file_type: systemVerilogSource
generate:
@@ -30,7 +30,7 @@
- files_formal
generate:
- csr_assert_gen
- toplevel: pinmux_fpv
+ toplevel: pinmux_tb
formal:
<<: *default_target
diff --git a/hw/ip/pinmux/fpv/tb/pinmux_fpv.sv b/hw/ip/pinmux/fpv/tb/pinmux_tb.sv
similarity index 96%
rename from hw/ip/pinmux/fpv/tb/pinmux_fpv.sv
rename to hw/ip/pinmux/fpv/tb/pinmux_tb.sv
index 46ab3d7..042cda4 100644
--- a/hw/ip/pinmux/fpv/tb/pinmux_fpv.sv
+++ b/hw/ip/pinmux/fpv/tb/pinmux_tb.sv
@@ -4,7 +4,7 @@
//
// Testbench module for pinmux. Intended to use with a formal tool.
-module pinmux_fpv (
+module pinmux_tb (
input clk_i,
input rst_ni,
input tlul_pkg::tl_h2d_t tl_i,
@@ -33,4 +33,4 @@
.mio_in_i
);
-endmodule : pinmux_fpv
+endmodule : pinmux_tb
diff --git a/hw/ip/prim/fpv/prim_alert_rxtx_async_fatal_fpv.core b/hw/ip/prim/fpv/prim_alert_rxtx_async_fatal_fpv.core
index e9c5fdf..677a3fe 100644
--- a/hw/ip/prim/fpv/prim_alert_rxtx_async_fatal_fpv.core
+++ b/hw/ip/prim/fpv/prim_alert_rxtx_async_fatal_fpv.core
@@ -11,7 +11,7 @@
- lowrisc:prim:alert
files:
- vip/prim_alert_rxtx_async_assert_fpv.sv
- - tb/prim_alert_rxtx_async_fatal_fpv.sv
+ - tb/prim_alert_rxtx_async_fatal_tb.sv
- tb/prim_alert_rxtx_async_fatal_bind_fpv.sv
file_type: systemVerilogSource
@@ -23,7 +23,7 @@
filesets:
- files_formal
toplevel:
- - prim_alert_rxtx_async_fatal_fpv
+ - prim_alert_rxtx_async_fatal_tb
formal:
<<: *default_target
diff --git a/hw/ip/prim/fpv/prim_alert_rxtx_async_fpv.core b/hw/ip/prim/fpv/prim_alert_rxtx_async_fpv.core
index 77c630d..c1907fe 100644
--- a/hw/ip/prim/fpv/prim_alert_rxtx_async_fpv.core
+++ b/hw/ip/prim/fpv/prim_alert_rxtx_async_fpv.core
@@ -11,7 +11,7 @@
- lowrisc:prim:alert
files:
- vip/prim_alert_rxtx_async_assert_fpv.sv
- - tb/prim_alert_rxtx_async_fpv.sv
+ - tb/prim_alert_rxtx_async_tb.sv
- tb/prim_alert_rxtx_async_bind_fpv.sv
file_type: systemVerilogSource
@@ -23,7 +23,7 @@
filesets:
- files_formal
toplevel:
- - prim_alert_rxtx_async_fpv
+ - prim_alert_rxtx_async_tb
formal:
<<: *default_target
diff --git a/hw/ip/prim/fpv/prim_alert_rxtx_fatal_fpv.core b/hw/ip/prim/fpv/prim_alert_rxtx_fatal_fpv.core
index bcab444..28a286c 100644
--- a/hw/ip/prim/fpv/prim_alert_rxtx_fatal_fpv.core
+++ b/hw/ip/prim/fpv/prim_alert_rxtx_fatal_fpv.core
@@ -11,7 +11,7 @@
- lowrisc:prim:alert
files:
- vip/prim_alert_rxtx_assert_fpv.sv
- - tb/prim_alert_rxtx_fatal_fpv.sv
+ - tb/prim_alert_rxtx_fatal_tb.sv
- tb/prim_alert_rxtx_fatal_bind_fpv.sv
file_type: systemVerilogSource
@@ -23,7 +23,7 @@
filesets:
- files_formal
toplevel:
- - prim_alert_rxtx_fatal_fpv
+ - prim_alert_rxtx_fatal_tb
formal:
<<: *default_target
diff --git a/hw/ip/prim/fpv/prim_alert_rxtx_fpv.core b/hw/ip/prim/fpv/prim_alert_rxtx_fpv.core
index 65e9c9e..8c87903 100644
--- a/hw/ip/prim/fpv/prim_alert_rxtx_fpv.core
+++ b/hw/ip/prim/fpv/prim_alert_rxtx_fpv.core
@@ -11,7 +11,7 @@
- lowrisc:prim:alert
files:
- vip/prim_alert_rxtx_assert_fpv.sv
- - tb/prim_alert_rxtx_fpv.sv
+ - tb/prim_alert_rxtx_tb.sv
- tb/prim_alert_rxtx_bind_fpv.sv
file_type: systemVerilogSource
@@ -23,7 +23,7 @@
filesets:
- files_formal
toplevel:
- - prim_alert_rxtx_fpv
+ - prim_alert_rxtx_tb
formal:
<<: *default_target
diff --git a/hw/ip/prim/fpv/prim_arbiter_fixed_fpv.core b/hw/ip/prim/fpv/prim_arbiter_fixed_fpv.core
index 4b3359b..e133422 100644
--- a/hw/ip/prim/fpv/prim_arbiter_fixed_fpv.core
+++ b/hw/ip/prim/fpv/prim_arbiter_fixed_fpv.core
@@ -9,7 +9,7 @@
depend:
- lowrisc:prim:all
files:
- - tb/prim_arbiter_fixed_fpv.sv
+ - tb/prim_arbiter_fixed_tb.sv
file_type: systemVerilogSource
targets:
@@ -19,7 +19,7 @@
default_tool: icarus
filesets:
- files_formal
- toplevel: prim_arbiter_fixed_fpv
+ toplevel: prim_arbiter_fixed_tb
formal:
<<: *default_target
diff --git a/hw/ip/prim/fpv/prim_arbiter_ppc_fpv.core b/hw/ip/prim/fpv/prim_arbiter_ppc_fpv.core
index aad2830..48c8835 100644
--- a/hw/ip/prim/fpv/prim_arbiter_ppc_fpv.core
+++ b/hw/ip/prim/fpv/prim_arbiter_ppc_fpv.core
@@ -9,7 +9,7 @@
depend:
- lowrisc:prim:all
files:
- - tb/prim_arbiter_ppc_fpv.sv
+ - tb/prim_arbiter_ppc_tb.sv
file_type: systemVerilogSource
targets:
@@ -19,7 +19,7 @@
default_tool: icarus
filesets:
- files_formal
- toplevel: prim_arbiter_ppc_fpv
+ toplevel: prim_arbiter_ppc_tb
formal:
<<: *default_target
diff --git a/hw/ip/prim/fpv/prim_arbiter_tree_fpv.core b/hw/ip/prim/fpv/prim_arbiter_tree_fpv.core
index 72abea8..684d5c3 100644
--- a/hw/ip/prim/fpv/prim_arbiter_tree_fpv.core
+++ b/hw/ip/prim/fpv/prim_arbiter_tree_fpv.core
@@ -9,7 +9,7 @@
depend:
- lowrisc:prim:all
files:
- - tb/prim_arbiter_tree_fpv.sv
+ - tb/prim_arbiter_tree_tb.sv
file_type: systemVerilogSource
targets:
@@ -19,7 +19,7 @@
default_tool: icarus
filesets:
- files_formal
- toplevel: prim_arbiter_tree_fpv
+ toplevel: prim_arbiter_tree_tb
formal:
<<: *default_target
diff --git a/hw/ip/prim/fpv/prim_esc_rxtx_fpv.core b/hw/ip/prim/fpv/prim_esc_rxtx_fpv.core
index 80b5562..7538ca3 100644
--- a/hw/ip/prim/fpv/prim_esc_rxtx_fpv.core
+++ b/hw/ip/prim/fpv/prim_esc_rxtx_fpv.core
@@ -12,7 +12,7 @@
files:
- vip/prim_esc_rxtx_assert_fpv.sv
- tb/prim_esc_rxtx_bind_fpv.sv
- - tb/prim_esc_rxtx_fpv.sv
+ - tb/prim_esc_rxtx_tb.sv
file_type: systemVerilogSource
targets:
@@ -23,7 +23,7 @@
filesets:
- files_formal
toplevel:
- - prim_esc_rxtx_fpv
+ - prim_esc_rxtx_tb
formal:
<<: *default_target
diff --git a/hw/ip/prim/fpv/prim_fifo_async_sram_adapter_fpv.core b/hw/ip/prim/fpv/prim_fifo_async_sram_adapter_fpv.core
index 1b546d8..4c8c924 100644
--- a/hw/ip/prim/fpv/prim_fifo_async_sram_adapter_fpv.core
+++ b/hw/ip/prim/fpv/prim_fifo_async_sram_adapter_fpv.core
@@ -10,7 +10,7 @@
- lowrisc:prim:all
- lowrisc:prim:ram_2p_async_adv
files:
- - tb/prim_fifo_async_sram_adapter_fpv.sv
+ - tb/prim_fifo_async_sram_adapter_tb.sv
file_type: systemVerilogSource
targets:
@@ -18,7 +18,7 @@
default_tool: icarus
filesets:
- files_formal
- toplevel: prim_fifo_async_sram_adapter_fpv
+ toplevel: prim_fifo_async_sram_adapter_tb
formal:
<<: *default_target
diff --git a/hw/ip/prim/fpv/prim_fifo_sync_fpv.core b/hw/ip/prim/fpv/prim_fifo_sync_fpv.core
index 79bb7fa..d3f1baa 100644
--- a/hw/ip/prim/fpv/prim_fifo_sync_fpv.core
+++ b/hw/ip/prim/fpv/prim_fifo_sync_fpv.core
@@ -11,7 +11,7 @@
files:
- vip/prim_fifo_sync_assert_fpv.sv
- tb/prim_fifo_sync_bind_fpv.sv
- - tb/prim_fifo_sync_fpv.sv
+ - tb/prim_fifo_sync_tb.sv
file_type: systemVerilogSource
targets:
@@ -21,7 +21,7 @@
default_tool: icarus
filesets:
- files_formal
- toplevel: prim_fifo_sync_fpv
+ toplevel: prim_fifo_sync_tb
formal:
<<: *default_target
diff --git a/hw/ip/prim/fpv/prim_keccak_fpv.core b/hw/ip/prim/fpv/prim_keccak_fpv.core
index 13a4541..b60df13 100644
--- a/hw/ip/prim/fpv/prim_keccak_fpv.core
+++ b/hw/ip/prim/fpv/prim_keccak_fpv.core
@@ -9,7 +9,7 @@
depend:
- lowrisc:prim:all
files:
- - tb/prim_keccak_fpv.sv
+ - tb/prim_keccak_tb.sv
file_type: systemVerilogSource
targets:
@@ -20,7 +20,7 @@
filesets:
- files_fpv
toplevel:
- - prim_keccak_fpv
+ - prim_keccak_tb
lint:
<<: *default_target
diff --git a/hw/ip/prim/fpv/prim_lfsr_fpv.core b/hw/ip/prim/fpv/prim_lfsr_fpv.core
index 394d306..824f212 100644
--- a/hw/ip/prim/fpv/prim_lfsr_fpv.core
+++ b/hw/ip/prim/fpv/prim_lfsr_fpv.core
@@ -9,7 +9,7 @@
depend:
- lowrisc:prim:lfsr
files:
- - tb/prim_lfsr_fpv.sv
+ - tb/prim_lfsr_tb.sv
file_type: systemVerilogSource
targets:
@@ -20,7 +20,7 @@
filesets:
- files_formal
toplevel:
- - prim_lfsr_fpv
+ - prim_lfsr_tb
formal:
<<: *default_target
diff --git a/hw/ip/prim/fpv/prim_packer_fpv.core b/hw/ip/prim/fpv/prim_packer_fpv.core
index 73c521e..3e147f7 100644
--- a/hw/ip/prim/fpv/prim_packer_fpv.core
+++ b/hw/ip/prim/fpv/prim_packer_fpv.core
@@ -10,7 +10,7 @@
depend:
- lowrisc:prim:all
files:
- - tb/prim_packer_fpv.sv
+ - tb/prim_packer_tb.sv
file_type: systemVerilogSource
targets:
@@ -20,7 +20,7 @@
default_tool: icarus
filesets:
- files_formal
- toplevel: prim_packer_fpv
+ toplevel: prim_packer_tb
formal:
<<: *default_target
diff --git a/hw/ip/prim/fpv/prim_secded_22_16_fpv.core b/hw/ip/prim/fpv/prim_secded_22_16_fpv.core
index 5ed01f1..5d9ab39 100644
--- a/hw/ip/prim/fpv/prim_secded_22_16_fpv.core
+++ b/hw/ip/prim/fpv/prim_secded_22_16_fpv.core
@@ -11,7 +11,7 @@
- lowrisc:prim:secded
files:
- vip/prim_secded_22_16_assert_fpv.sv
- - tb/prim_secded_22_16_fpv.sv
+ - tb/prim_secded_22_16_tb.sv
- tb/prim_secded_22_16_bind_fpv.sv
file_type: systemVerilogSource
@@ -23,7 +23,7 @@
filesets:
- files_formal
toplevel:
- - prim_secded_22_16_fpv
+ - prim_secded_22_16_tb
formal:
<<: *default_target
diff --git a/hw/ip/prim/fpv/prim_secded_28_22_fpv.core b/hw/ip/prim/fpv/prim_secded_28_22_fpv.core
index 12f868a..97f4f4e 100644
--- a/hw/ip/prim/fpv/prim_secded_28_22_fpv.core
+++ b/hw/ip/prim/fpv/prim_secded_28_22_fpv.core
@@ -11,7 +11,7 @@
- lowrisc:prim:secded
files:
- vip/prim_secded_28_22_assert_fpv.sv
- - tb/prim_secded_28_22_fpv.sv
+ - tb/prim_secded_28_22_tb.sv
- tb/prim_secded_28_22_bind_fpv.sv
file_type: systemVerilogSource
@@ -23,7 +23,7 @@
filesets:
- files_formal
toplevel:
- - prim_secded_28_22_fpv
+ - prim_secded_28_22_tb
formal:
<<: *default_target
diff --git a/hw/ip/prim/fpv/prim_secded_39_32_fpv.core b/hw/ip/prim/fpv/prim_secded_39_32_fpv.core
index 85650dc..c239151 100644
--- a/hw/ip/prim/fpv/prim_secded_39_32_fpv.core
+++ b/hw/ip/prim/fpv/prim_secded_39_32_fpv.core
@@ -11,7 +11,7 @@
- lowrisc:prim:secded
files:
- vip/prim_secded_39_32_assert_fpv.sv
- - tb/prim_secded_39_32_fpv.sv
+ - tb/prim_secded_39_32_tb.sv
- tb/prim_secded_39_32_bind_fpv.sv
file_type: systemVerilogSource
@@ -23,7 +23,7 @@
filesets:
- files_formal
toplevel:
- - prim_secded_39_32_fpv
+ - prim_secded_39_32_tb
formal:
<<: *default_target
diff --git a/hw/ip/prim/fpv/prim_secded_64_57_fpv.core b/hw/ip/prim/fpv/prim_secded_64_57_fpv.core
index 890cf29..2ab02bc 100644
--- a/hw/ip/prim/fpv/prim_secded_64_57_fpv.core
+++ b/hw/ip/prim/fpv/prim_secded_64_57_fpv.core
@@ -11,7 +11,7 @@
- lowrisc:prim:secded
files:
- vip/prim_secded_64_57_assert_fpv.sv
- - tb/prim_secded_64_57_fpv.sv
+ - tb/prim_secded_64_57_tb.sv
- tb/prim_secded_64_57_bind_fpv.sv
file_type: systemVerilogSource
@@ -23,7 +23,7 @@
filesets:
- files_formal
toplevel:
- - prim_secded_64_57_fpv
+ - prim_secded_64_57_tb
formal:
<<: *default_target
diff --git a/hw/ip/prim/fpv/prim_secded_72_64_fpv.core b/hw/ip/prim/fpv/prim_secded_72_64_fpv.core
index d58bf13..cc5aeb8 100644
--- a/hw/ip/prim/fpv/prim_secded_72_64_fpv.core
+++ b/hw/ip/prim/fpv/prim_secded_72_64_fpv.core
@@ -11,7 +11,7 @@
- lowrisc:prim:secded
files:
- vip/prim_secded_72_64_assert_fpv.sv
- - tb/prim_secded_72_64_fpv.sv
+ - tb/prim_secded_72_64_tb.sv
- tb/prim_secded_72_64_bind_fpv.sv
file_type: systemVerilogSource
@@ -23,7 +23,7 @@
filesets:
- files_formal
toplevel:
- - prim_secded_72_64_fpv
+ - prim_secded_72_64_tb
formal:
<<: *default_target
diff --git a/hw/ip/prim/fpv/prim_secded_hamming_22_16_fpv.core b/hw/ip/prim/fpv/prim_secded_hamming_22_16_fpv.core
index 07b2e2b..4910804 100644
--- a/hw/ip/prim/fpv/prim_secded_hamming_22_16_fpv.core
+++ b/hw/ip/prim/fpv/prim_secded_hamming_22_16_fpv.core
@@ -11,7 +11,7 @@
- lowrisc:prim:secded
files:
- vip/prim_secded_hamming_22_16_assert_fpv.sv
- - tb/prim_secded_hamming_22_16_fpv.sv
+ - tb/prim_secded_hamming_22_16_tb.sv
- tb/prim_secded_hamming_22_16_bind_fpv.sv
file_type: systemVerilogSource
@@ -23,7 +23,7 @@
filesets:
- files_formal
toplevel:
- - prim_secded_hamming_22_16_fpv
+ - prim_secded_hamming_22_16_tb
formal:
<<: *default_target
diff --git a/hw/ip/prim/fpv/prim_secded_hamming_39_32_fpv.core b/hw/ip/prim/fpv/prim_secded_hamming_39_32_fpv.core
index f6a0846..b73f22b 100644
--- a/hw/ip/prim/fpv/prim_secded_hamming_39_32_fpv.core
+++ b/hw/ip/prim/fpv/prim_secded_hamming_39_32_fpv.core
@@ -11,7 +11,7 @@
- lowrisc:prim:secded
files:
- vip/prim_secded_hamming_39_32_assert_fpv.sv
- - tb/prim_secded_hamming_39_32_fpv.sv
+ - tb/prim_secded_hamming_39_32_tb.sv
- tb/prim_secded_hamming_39_32_bind_fpv.sv
file_type: systemVerilogSource
@@ -23,7 +23,7 @@
filesets:
- files_formal
toplevel:
- - prim_secded_hamming_39_32_fpv
+ - prim_secded_hamming_39_32_tb
formal:
<<: *default_target
diff --git a/hw/ip/prim/fpv/prim_secded_hamming_72_64_fpv.core b/hw/ip/prim/fpv/prim_secded_hamming_72_64_fpv.core
index caaa10b..5f9f102 100644
--- a/hw/ip/prim/fpv/prim_secded_hamming_72_64_fpv.core
+++ b/hw/ip/prim/fpv/prim_secded_hamming_72_64_fpv.core
@@ -11,7 +11,7 @@
- lowrisc:prim:secded
files:
- vip/prim_secded_hamming_72_64_assert_fpv.sv
- - tb/prim_secded_hamming_72_64_fpv.sv
+ - tb/prim_secded_hamming_72_64_tb.sv
- tb/prim_secded_hamming_72_64_bind_fpv.sv
file_type: systemVerilogSource
@@ -23,7 +23,7 @@
filesets:
- files_formal
toplevel:
- - prim_secded_hamming_72_64_fpv
+ - prim_secded_hamming_72_64_tb
formal:
<<: *default_target
diff --git a/hw/ip/prim/fpv/tb/prim_alert_rxtx_async_fatal_fpv.sv b/hw/ip/prim/fpv/tb/prim_alert_rxtx_async_fatal_tb.sv
similarity index 97%
rename from hw/ip/prim/fpv/tb/prim_alert_rxtx_async_fatal_fpv.sv
rename to hw/ip/prim/fpv/tb/prim_alert_rxtx_async_fatal_tb.sv
index b6f51cb..e6aea4b 100644
--- a/hw/ip/prim/fpv/tb/prim_alert_rxtx_async_fatal_fpv.sv
+++ b/hw/ip/prim/fpv/tb/prim_alert_rxtx_async_fatal_tb.sv
@@ -5,7 +5,7 @@
// Testbench module for alert sender/receiver pair. Intended to use with
// a formal tool.
-module prim_alert_rxtx_async_fatal_fpv
+module prim_alert_rxtx_async_fatal_tb
import prim_alert_pkg::*;
import prim_mubi_pkg::mubi4_t;
(
@@ -116,4 +116,4 @@
end
end
-endmodule : prim_alert_rxtx_async_fatal_fpv
+endmodule : prim_alert_rxtx_async_fatal_tb
diff --git a/hw/ip/prim/fpv/tb/prim_alert_rxtx_async_fpv.sv b/hw/ip/prim/fpv/tb/prim_alert_rxtx_async_tb.sv
similarity index 97%
rename from hw/ip/prim/fpv/tb/prim_alert_rxtx_async_fpv.sv
rename to hw/ip/prim/fpv/tb/prim_alert_rxtx_async_tb.sv
index a64d5b7..0327985 100644
--- a/hw/ip/prim/fpv/tb/prim_alert_rxtx_async_fpv.sv
+++ b/hw/ip/prim/fpv/tb/prim_alert_rxtx_async_tb.sv
@@ -5,7 +5,7 @@
// Testbench module for alert sender/receiver pair. Intended to use with
// a formal tool.
-module prim_alert_rxtx_async_fpv
+module prim_alert_rxtx_async_tb
import prim_alert_pkg::*;
import prim_mubi_pkg::mubi4_t;
(
@@ -117,4 +117,4 @@
end
end
-endmodule : prim_alert_rxtx_async_fpv
+endmodule : prim_alert_rxtx_async_tb
diff --git a/hw/ip/prim/fpv/tb/prim_alert_rxtx_fatal_fpv.sv b/hw/ip/prim/fpv/tb/prim_alert_rxtx_fatal_tb.sv
similarity index 96%
rename from hw/ip/prim/fpv/tb/prim_alert_rxtx_fatal_fpv.sv
rename to hw/ip/prim/fpv/tb/prim_alert_rxtx_fatal_tb.sv
index 46df21d..86376d2 100644
--- a/hw/ip/prim/fpv/tb/prim_alert_rxtx_fatal_fpv.sv
+++ b/hw/ip/prim/fpv/tb/prim_alert_rxtx_fatal_tb.sv
@@ -5,7 +5,7 @@
// Testbench module for alert sender/receiver pair. Intended to use with
// a formal tool.
-module prim_alert_rxtx_fatal_fpv
+module prim_alert_rxtx_fatal_tb
import prim_alert_pkg::*;
import prim_mubi_pkg::mubi4_t;
(
@@ -73,4 +73,4 @@
.alert_tx_i ( alert_tx_in )
);
-endmodule : prim_alert_rxtx_fatal_fpv
+endmodule : prim_alert_rxtx_fatal_tb
diff --git a/hw/ip/prim/fpv/tb/prim_alert_rxtx_fpv.sv b/hw/ip/prim/fpv/tb/prim_alert_rxtx_tb.sv
similarity index 96%
rename from hw/ip/prim/fpv/tb/prim_alert_rxtx_fpv.sv
rename to hw/ip/prim/fpv/tb/prim_alert_rxtx_tb.sv
index 741829b..a7575af 100644
--- a/hw/ip/prim/fpv/tb/prim_alert_rxtx_fpv.sv
+++ b/hw/ip/prim/fpv/tb/prim_alert_rxtx_tb.sv
@@ -5,7 +5,7 @@
// Testbench module for alert sender/receiver pair. Intended to use with
// a formal tool.
-module prim_alert_rxtx_fpv
+module prim_alert_rxtx_tb
import prim_alert_pkg::*;
import prim_mubi_pkg::mubi4_t;
(
@@ -73,4 +73,4 @@
.alert_tx_i ( alert_tx_in )
);
-endmodule : prim_alert_rxtx_fpv
+endmodule : prim_alert_rxtx_tb
diff --git a/hw/ip/prim/fpv/tb/prim_arbiter_fixed_fpv.sv b/hw/ip/prim/fpv/tb/prim_arbiter_fixed_tb.sv
similarity index 91%
rename from hw/ip/prim/fpv/tb/prim_arbiter_fixed_fpv.sv
rename to hw/ip/prim/fpv/tb/prim_arbiter_fixed_tb.sv
index b21a1b2..be7a572 100644
--- a/hw/ip/prim/fpv/tb/prim_arbiter_fixed_fpv.sv
+++ b/hw/ip/prim/fpv/tb/prim_arbiter_fixed_tb.sv
@@ -5,7 +5,7 @@
// Testbench module for prim_arbiter_fixed.
// Intended to be used with a formal tool.
-module prim_arbiter_fixed_fpv #(
+module prim_arbiter_fixed_tb #(
parameter int N = 8,
parameter int DW = 32,
parameter bit EnDataPort = 1,
@@ -40,4 +40,4 @@
);
-endmodule : prim_arbiter_fixed_fpv
+endmodule : prim_arbiter_fixed_tb
diff --git a/hw/ip/prim/fpv/tb/prim_arbiter_ppc_fpv.sv b/hw/ip/prim/fpv/tb/prim_arbiter_ppc_tb.sv
similarity index 93%
rename from hw/ip/prim/fpv/tb/prim_arbiter_ppc_fpv.sv
rename to hw/ip/prim/fpv/tb/prim_arbiter_ppc_tb.sv
index a571992..087b2dd 100644
--- a/hw/ip/prim/fpv/tb/prim_arbiter_ppc_fpv.sv
+++ b/hw/ip/prim/fpv/tb/prim_arbiter_ppc_tb.sv
@@ -5,7 +5,7 @@
// Testbench module for prim_arbiter_ppc.
// Intended to be used with a formal tool.
-module prim_arbiter_ppc_fpv #(
+module prim_arbiter_ppc_tb #(
parameter int unsigned N = 8,
parameter int unsigned DW = 32,
parameter bit EnDataPort = 1,
@@ -15,12 +15,10 @@
input rst_ni,
input req_chk_i,
-
input [ N-1:0] req_i,
input [DW-1:0] data_i [N],
output logic [ N-1:0] gnt_o,
output logic [IdxW-1:0] idx_o,
-
output logic valid_o,
output logic [DW-1:0] data_o,
input ready_i
@@ -45,4 +43,4 @@
);
-endmodule : prim_arbiter_ppc_fpv
+endmodule : prim_arbiter_ppc_tb
diff --git a/hw/ip/prim/fpv/tb/prim_arbiter_tree_fpv.sv b/hw/ip/prim/fpv/tb/prim_arbiter_tree_tb.sv
similarity index 92%
rename from hw/ip/prim/fpv/tb/prim_arbiter_tree_fpv.sv
rename to hw/ip/prim/fpv/tb/prim_arbiter_tree_tb.sv
index b5a61c2..d37ea88 100644
--- a/hw/ip/prim/fpv/tb/prim_arbiter_tree_fpv.sv
+++ b/hw/ip/prim/fpv/tb/prim_arbiter_tree_tb.sv
@@ -5,7 +5,7 @@
// Testbench module for prim_arbiter_tree.
// Intended to be used with a formal tool.
-module prim_arbiter_tree_fpv #(
+module prim_arbiter_tree_tb #(
parameter int N = 8,
parameter int DW = 32,
parameter bit EnDataPort = 1,
@@ -15,12 +15,10 @@
input rst_ni,
input req_chk_i,
-
input [ N-1:0] req_i,
input [DW-1:0] data_i [N],
output logic [ N-1:0] gnt_o,
output logic [IdxW-1:0] idx_o,
-
output logic valid_o,
output logic [DW-1:0] data_o,
input ready_i
@@ -45,4 +43,4 @@
);
-endmodule : prim_arbiter_tree_fpv
+endmodule : prim_arbiter_tree_tb
diff --git a/hw/ip/prim/fpv/tb/prim_esc_rxtx_fpv.sv b/hw/ip/prim/fpv/tb/prim_esc_rxtx_tb.sv
similarity index 95%
rename from hw/ip/prim/fpv/tb/prim_esc_rxtx_fpv.sv
rename to hw/ip/prim/fpv/tb/prim_esc_rxtx_tb.sv
index c9a17d4..7e27902 100644
--- a/hw/ip/prim/fpv/tb/prim_esc_rxtx_fpv.sv
+++ b/hw/ip/prim/fpv/tb/prim_esc_rxtx_tb.sv
@@ -5,7 +5,7 @@
// Testbench module for escalation sender/receiver pair. Intended to use with
// a formal tool.
-module prim_esc_rxtx_fpv
+module prim_esc_rxtx_tb
import prim_esc_pkg::*;
(
input clk_i,
@@ -54,4 +54,4 @@
.esc_tx_i ( esc_tx_in )
);
-endmodule : prim_esc_rxtx_fpv
+endmodule : prim_esc_rxtx_tb
diff --git a/hw/ip/prim/fpv/tb/prim_fifo_async_sram_adapter_fpv.sv b/hw/ip/prim/fpv/tb/prim_fifo_async_sram_adapter_tb.sv
similarity index 97%
rename from hw/ip/prim/fpv/tb/prim_fifo_async_sram_adapter_fpv.sv
rename to hw/ip/prim/fpv/tb/prim_fifo_async_sram_adapter_tb.sv
index fb3dda9..889796e 100644
--- a/hw/ip/prim/fpv/tb/prim_fifo_async_sram_adapter_fpv.sv
+++ b/hw/ip/prim/fpv/tb/prim_fifo_async_sram_adapter_tb.sv
@@ -4,7 +4,7 @@
//
// Testbench module for prim_fifo_sram_async
-module prim_fifo_async_sram_adapter_fpv #(
+module prim_fifo_async_sram_adapter_tb #(
parameter int unsigned Width = 32,
parameter int unsigned Depth = 16,
@@ -201,4 +201,4 @@
clk_rd_i, !rst_ni)
`endif // FPV_ON
-endmodule : prim_fifo_async_sram_adapter_fpv
+endmodule : prim_fifo_async_sram_adapter_tb
diff --git a/hw/ip/prim/fpv/tb/prim_fifo_sync_fpv.sv b/hw/ip/prim/fpv/tb/prim_fifo_sync_tb.sv
similarity index 98%
rename from hw/ip/prim/fpv/tb/prim_fifo_sync_fpv.sv
rename to hw/ip/prim/fpv/tb/prim_fifo_sync_tb.sv
index 808df8b..5dfa5bc 100644
--- a/hw/ip/prim/fpv/tb/prim_fifo_sync_fpv.sv
+++ b/hw/ip/prim/fpv/tb/prim_fifo_sync_tb.sv
@@ -14,7 +14,7 @@
// Data/depth value checks are enabled up to depth 8 in order to constrain the
// runtime.
-module prim_fifo_sync_fpv #(
+module prim_fifo_sync_tb #(
// number of DUTs instantiated in this FPV testbench
parameter int unsigned NumDuts = 11,
// fifo params
@@ -233,4 +233,4 @@
.depth_o(depth_o[10][4:0])
);
-endmodule : prim_fifo_sync_fpv
+endmodule : prim_fifo_sync_tb
diff --git a/hw/ip/prim/fpv/tb/prim_keccak_fpv.sv b/hw/ip/prim/fpv/tb/prim_keccak_tb.sv
similarity index 98%
rename from hw/ip/prim/fpv/tb/prim_keccak_fpv.sv
rename to hw/ip/prim/fpv/tb/prim_keccak_tb.sv
index 78cb994..f5d0c3d 100644
--- a/hw/ip/prim/fpv/tb/prim_keccak_fpv.sv
+++ b/hw/ip/prim/fpv/tb/prim_keccak_tb.sv
@@ -4,7 +4,7 @@
//
// Testbench module for prim_keccak. Intended to be used with a formal tool.
-module prim_keccak_fpv #(
+module prim_keccak_tb #(
parameter int Width = 1600
) (
input clk_i,
diff --git a/hw/ip/prim/fpv/tb/prim_lfsr_fpv.sv b/hw/ip/prim/fpv/tb/prim_lfsr_tb.sv
similarity index 98%
rename from hw/ip/prim/fpv/tb/prim_lfsr_fpv.sv
rename to hw/ip/prim/fpv/tb/prim_lfsr_tb.sv
index 0e3e9a6..dd2c9eb 100644
--- a/hw/ip/prim/fpv/tb/prim_lfsr_fpv.sv
+++ b/hw/ip/prim/fpv/tb/prim_lfsr_tb.sv
@@ -4,7 +4,7 @@
//
// Testbench module for prim_lfsr. Intended to be used with a formal tool.
-module prim_lfsr_fpv #(
+module prim_lfsr_tb #(
// LFSR entropy and output bitwidths (set to 1 here as they are unused)
parameter int unsigned EntropyDw = 1,
parameter int unsigned StateOutDw = 1,
@@ -120,4 +120,4 @@
);
end
-endmodule : prim_lfsr_fpv
+endmodule : prim_lfsr_tb
diff --git a/hw/ip/prim/fpv/tb/prim_packer_fpv.sv b/hw/ip/prim/fpv/tb/prim_packer_tb.sv
similarity index 96%
rename from hw/ip/prim/fpv/tb/prim_packer_fpv.sv
rename to hw/ip/prim/fpv/tb/prim_packer_tb.sv
index 4753199..d666386 100644
--- a/hw/ip/prim/fpv/tb/prim_packer_fpv.sv
+++ b/hw/ip/prim/fpv/tb/prim_packer_tb.sv
@@ -5,7 +5,7 @@
// Testbench module for prim_packer. Intended to be used with a formal tool.
// To reduce the runtime for prim_packer, we limited the width parameter.
-module prim_packer_fpv #(
+module prim_packer_tb #(
parameter int unsigned MaxInW = 64,
parameter int unsigned MaxOutW = 64
) (
@@ -60,4 +60,4 @@
.flush_done_o
);
-endmodule : prim_packer_fpv
+endmodule : prim_packer_tb
diff --git a/hw/ip/prim/fpv/tb/prim_secded_22_16_fpv.sv b/hw/ip/prim/fpv/tb/prim_secded_22_16_tb.sv
similarity index 91%
rename from hw/ip/prim/fpv/tb/prim_secded_22_16_fpv.sv
rename to hw/ip/prim/fpv/tb/prim_secded_22_16_tb.sv
index 46dfb16..7a334b3 100644
--- a/hw/ip/prim/fpv/tb/prim_secded_22_16_fpv.sv
+++ b/hw/ip/prim/fpv/tb/prim_secded_22_16_tb.sv
@@ -4,7 +4,7 @@
//
// SECDED FPV testbench generated by util/design/secded_gen.py
-module prim_secded_22_16_fpv (
+module prim_secded_22_16_tb (
input clk_i,
input rst_ni,
input [15:0] data_i,
@@ -28,4 +28,4 @@
.err_o
);
-endmodule : prim_secded_22_16_fpv
+endmodule : prim_secded_22_16_tb
diff --git a/hw/ip/prim/fpv/tb/prim_secded_28_22_fpv.sv b/hw/ip/prim/fpv/tb/prim_secded_28_22_tb.sv
similarity index 91%
rename from hw/ip/prim/fpv/tb/prim_secded_28_22_fpv.sv
rename to hw/ip/prim/fpv/tb/prim_secded_28_22_tb.sv
index d2db256..2a3c0cb 100644
--- a/hw/ip/prim/fpv/tb/prim_secded_28_22_fpv.sv
+++ b/hw/ip/prim/fpv/tb/prim_secded_28_22_tb.sv
@@ -4,7 +4,7 @@
//
// SECDED FPV testbench generated by util/design/secded_gen.py
-module prim_secded_28_22_fpv (
+module prim_secded_28_22_tb (
input clk_i,
input rst_ni,
input [21:0] data_i,
@@ -28,4 +28,4 @@
.err_o
);
-endmodule : prim_secded_28_22_fpv
+endmodule : prim_secded_28_22_tb
diff --git a/hw/ip/prim/fpv/tb/prim_secded_39_32_fpv.sv b/hw/ip/prim/fpv/tb/prim_secded_39_32_tb.sv
similarity index 91%
rename from hw/ip/prim/fpv/tb/prim_secded_39_32_fpv.sv
rename to hw/ip/prim/fpv/tb/prim_secded_39_32_tb.sv
index 34fbf2a..6dc9b70 100644
--- a/hw/ip/prim/fpv/tb/prim_secded_39_32_fpv.sv
+++ b/hw/ip/prim/fpv/tb/prim_secded_39_32_tb.sv
@@ -4,7 +4,7 @@
//
// SECDED FPV testbench generated by util/design/secded_gen.py
-module prim_secded_39_32_fpv (
+module prim_secded_39_32_tb (
input clk_i,
input rst_ni,
input [31:0] data_i,
@@ -28,4 +28,4 @@
.err_o
);
-endmodule : prim_secded_39_32_fpv
+endmodule : prim_secded_39_32_tb
diff --git a/hw/ip/prim/fpv/tb/prim_secded_64_57_fpv.sv b/hw/ip/prim/fpv/tb/prim_secded_64_57_tb.sv
similarity index 91%
rename from hw/ip/prim/fpv/tb/prim_secded_64_57_fpv.sv
rename to hw/ip/prim/fpv/tb/prim_secded_64_57_tb.sv
index 7b735a1..f32c811 100644
--- a/hw/ip/prim/fpv/tb/prim_secded_64_57_fpv.sv
+++ b/hw/ip/prim/fpv/tb/prim_secded_64_57_tb.sv
@@ -4,7 +4,7 @@
//
// SECDED FPV testbench generated by util/design/secded_gen.py
-module prim_secded_64_57_fpv (
+module prim_secded_64_57_tb (
input clk_i,
input rst_ni,
input [56:0] data_i,
@@ -28,4 +28,4 @@
.err_o
);
-endmodule : prim_secded_64_57_fpv
+endmodule : prim_secded_64_57_tb
diff --git a/hw/ip/prim/fpv/tb/prim_secded_72_64_fpv.sv b/hw/ip/prim/fpv/tb/prim_secded_72_64_tb.sv
similarity index 91%
rename from hw/ip/prim/fpv/tb/prim_secded_72_64_fpv.sv
rename to hw/ip/prim/fpv/tb/prim_secded_72_64_tb.sv
index 0e69780..543e29a 100644
--- a/hw/ip/prim/fpv/tb/prim_secded_72_64_fpv.sv
+++ b/hw/ip/prim/fpv/tb/prim_secded_72_64_tb.sv
@@ -4,7 +4,7 @@
//
// SECDED FPV testbench generated by util/design/secded_gen.py
-module prim_secded_72_64_fpv (
+module prim_secded_72_64_tb (
input clk_i,
input rst_ni,
input [63:0] data_i,
@@ -28,4 +28,4 @@
.err_o
);
-endmodule : prim_secded_72_64_fpv
+endmodule : prim_secded_72_64_tb
diff --git a/hw/ip/prim/fpv/tb/prim_secded_hamming_22_16_fpv.sv b/hw/ip/prim/fpv/tb/prim_secded_hamming_22_16_tb.sv
similarity index 89%
rename from hw/ip/prim/fpv/tb/prim_secded_hamming_22_16_fpv.sv
rename to hw/ip/prim/fpv/tb/prim_secded_hamming_22_16_tb.sv
index 9787c19..0ba0517 100644
--- a/hw/ip/prim/fpv/tb/prim_secded_hamming_22_16_fpv.sv
+++ b/hw/ip/prim/fpv/tb/prim_secded_hamming_22_16_tb.sv
@@ -4,7 +4,7 @@
//
// SECDED FPV testbench generated by util/design/secded_gen.py
-module prim_secded_hamming_22_16_fpv (
+module prim_secded_hamming_22_16_tb (
input clk_i,
input rst_ni,
input [15:0] data_i,
@@ -28,4 +28,4 @@
.err_o
);
-endmodule : prim_secded_hamming_22_16_fpv
+endmodule : prim_secded_hamming_22_16_tb
diff --git a/hw/ip/prim/fpv/tb/prim_secded_hamming_39_32_fpv.sv b/hw/ip/prim/fpv/tb/prim_secded_hamming_39_32_tb.sv
similarity index 89%
rename from hw/ip/prim/fpv/tb/prim_secded_hamming_39_32_fpv.sv
rename to hw/ip/prim/fpv/tb/prim_secded_hamming_39_32_tb.sv
index 1b8f8b7..b94d348 100644
--- a/hw/ip/prim/fpv/tb/prim_secded_hamming_39_32_fpv.sv
+++ b/hw/ip/prim/fpv/tb/prim_secded_hamming_39_32_tb.sv
@@ -4,7 +4,7 @@
//
// SECDED FPV testbench generated by util/design/secded_gen.py
-module prim_secded_hamming_39_32_fpv (
+module prim_secded_hamming_39_32_tb (
input clk_i,
input rst_ni,
input [31:0] data_i,
@@ -28,4 +28,4 @@
.err_o
);
-endmodule : prim_secded_hamming_39_32_fpv
+endmodule : prim_secded_hamming_39_32_tb
diff --git a/hw/ip/prim/fpv/tb/prim_secded_hamming_72_64_fpv.sv b/hw/ip/prim/fpv/tb/prim_secded_hamming_72_64_tb.sv
similarity index 89%
rename from hw/ip/prim/fpv/tb/prim_secded_hamming_72_64_fpv.sv
rename to hw/ip/prim/fpv/tb/prim_secded_hamming_72_64_tb.sv
index c8deaef..ae1faf6 100644
--- a/hw/ip/prim/fpv/tb/prim_secded_hamming_72_64_fpv.sv
+++ b/hw/ip/prim/fpv/tb/prim_secded_hamming_72_64_tb.sv
@@ -4,7 +4,7 @@
//
// SECDED FPV testbench generated by util/design/secded_gen.py
-module prim_secded_hamming_72_64_fpv (
+module prim_secded_hamming_72_64_tb (
input clk_i,
input rst_ni,
input [63:0] data_i,
@@ -28,4 +28,4 @@
.err_o
);
-endmodule : prim_secded_hamming_72_64_fpv
+endmodule : prim_secded_hamming_72_64_tb
diff --git a/hw/ip_templates/alert_handler/fpv/alert_handler_esc_timer_fpv.core.tpl b/hw/ip_templates/alert_handler/fpv/alert_handler_esc_timer_fpv.core.tpl
index 067b24d..ebee5b6 100644
--- a/hw/ip_templates/alert_handler/fpv/alert_handler_esc_timer_fpv.core.tpl
+++ b/hw/ip_templates/alert_handler/fpv/alert_handler_esc_timer_fpv.core.tpl
@@ -12,7 +12,7 @@
files:
- vip/alert_handler_esc_timer_assert_fpv.sv
- tb/alert_handler_esc_timer_bind_fpv.sv
- - tb/alert_handler_esc_timer_fpv.sv
+ - tb/alert_handler_esc_timer_tb.sv
file_type: systemVerilogSource
targets:
@@ -22,4 +22,4 @@
default_tool: icarus
filesets:
- files_fpv
- toplevel: alert_handler_esc_timer_fpv
+ toplevel: alert_handler_esc_timer_tb
diff --git a/hw/ip_templates/alert_handler/fpv/alert_handler_ping_timer_fpv.core.tpl b/hw/ip_templates/alert_handler/fpv/alert_handler_ping_timer_fpv.core.tpl
index 3461ca7..f583181 100644
--- a/hw/ip_templates/alert_handler/fpv/alert_handler_ping_timer_fpv.core.tpl
+++ b/hw/ip_templates/alert_handler/fpv/alert_handler_ping_timer_fpv.core.tpl
@@ -12,7 +12,7 @@
files:
- vip/alert_handler_ping_timer_assert_fpv.sv
- tb/alert_handler_ping_timer_bind_fpv.sv
- - tb/alert_handler_ping_timer_fpv.sv
+ - tb/alert_handler_ping_timer_tb.sv
file_type: systemVerilogSource
targets:
@@ -22,4 +22,4 @@
default_tool: icarus
filesets:
- files_fpv
- toplevel: alert_handler_ping_timer_fpv
+ toplevel: alert_handler_ping_timer_tb
diff --git a/hw/ip_templates/alert_handler/fpv/tb/alert_handler_esc_timer_fpv.sv b/hw/ip_templates/alert_handler/fpv/tb/alert_handler_esc_timer_tb.sv
similarity index 91%
rename from hw/ip_templates/alert_handler/fpv/tb/alert_handler_esc_timer_fpv.sv
rename to hw/ip_templates/alert_handler/fpv/tb/alert_handler_esc_timer_tb.sv
index f1847e5..25b641f 100644
--- a/hw/ip_templates/alert_handler/fpv/tb/alert_handler_esc_timer_fpv.sv
+++ b/hw/ip_templates/alert_handler/fpv/tb/alert_handler_esc_timer_tb.sv
@@ -5,7 +5,7 @@
// Testbench module for alert_handler_esc_timer.
// Intended to be used with a formal tool.
-module alert_handler_esc_timer_fpv import alert_pkg::*; (
+module alert_handler_esc_timer_tb import alert_pkg::*; (
input clk_i,
input rst_ni,
input en_i,
@@ -46,4 +46,4 @@
);
-endmodule : alert_handler_esc_timer_fpv
+endmodule : alert_handler_esc_timer_tb
diff --git a/hw/ip_templates/alert_handler/fpv/tb/alert_handler_ping_timer_fpv.sv b/hw/ip_templates/alert_handler/fpv/tb/alert_handler_ping_timer_tb.sv
similarity index 93%
rename from hw/ip_templates/alert_handler/fpv/tb/alert_handler_ping_timer_fpv.sv
rename to hw/ip_templates/alert_handler/fpv/tb/alert_handler_ping_timer_tb.sv
index ca18a84..2b85385 100644
--- a/hw/ip_templates/alert_handler/fpv/tb/alert_handler_ping_timer_fpv.sv
+++ b/hw/ip_templates/alert_handler/fpv/tb/alert_handler_ping_timer_tb.sv
@@ -5,7 +5,7 @@
// Testbench module for ping timer in alert handler. Intended to use with
// a formal tool.
-module alert_handler_ping_timer_fpv import alert_pkg::*; (
+module alert_handler_ping_timer_tb import alert_pkg::*; (
input clk_i,
input rst_ni,
output logic edn_req_o,
@@ -45,4 +45,4 @@
.esc_ping_fail_o
);
-endmodule : alert_handler_ping_timer_fpv
+endmodule : alert_handler_ping_timer_tb
diff --git a/hw/ip_templates/rv_plic/fpv/rv_plic_fpv.core.tpl b/hw/ip_templates/rv_plic/fpv/rv_plic_fpv.core.tpl
index 504a92e..7618065 100644
--- a/hw/ip_templates/rv_plic/fpv/rv_plic_fpv.core.tpl
+++ b/hw/ip_templates/rv_plic/fpv/rv_plic_fpv.core.tpl
@@ -14,7 +14,7 @@
- lowrisc:fpv:csr_assert_gen
files:
- tb/rv_plic_bind_fpv.sv
- - tb/rv_plic_fpv.sv
+ - tb/rv_plic_tb.sv
- vip/rv_plic_assert_fpv.sv
file_type: systemVerilogSource
@@ -35,7 +35,7 @@
- files_formal
generate:
- csr_assert_gen
- toplevel: rv_plic_fpv
+ toplevel: rv_plic_tb
formal:
<<: *default_target
diff --git a/hw/ip_templates/rv_plic/fpv/tb/rv_plic_fpv.sv b/hw/ip_templates/rv_plic/fpv/tb/rv_plic_tb.sv
similarity index 95%
rename from hw/ip_templates/rv_plic/fpv/tb/rv_plic_fpv.sv
rename to hw/ip_templates/rv_plic/fpv/tb/rv_plic_tb.sv
index c5b218f..37ebbf1 100644
--- a/hw/ip_templates/rv_plic/fpv/tb/rv_plic_fpv.sv
+++ b/hw/ip_templates/rv_plic/fpv/tb/rv_plic_tb.sv
@@ -4,7 +4,7 @@
//
// Testbench module for rv_plic. Intended to use with a formal tool.
-module rv_plic_fpv import rv_plic_reg_pkg::*; #(
+module rv_plic_tb import rv_plic_reg_pkg::*; #(
// test all implementations
localparam int unsigned NumInstances = 1
) (
@@ -37,4 +37,4 @@
.msip_o (msip_o[0])
);
-endmodule : rv_plic_fpv
+endmodule : rv_plic_tb
diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/fpv/alert_handler_esc_timer_fpv.core b/hw/top_earlgrey/ip_autogen/alert_handler/fpv/alert_handler_esc_timer_fpv.core
index abe18e8..f7d8ec2 100644
--- a/hw/top_earlgrey/ip_autogen/alert_handler/fpv/alert_handler_esc_timer_fpv.core
+++ b/hw/top_earlgrey/ip_autogen/alert_handler/fpv/alert_handler_esc_timer_fpv.core
@@ -12,7 +12,7 @@
files:
- vip/alert_handler_esc_timer_assert_fpv.sv
- tb/alert_handler_esc_timer_bind_fpv.sv
- - tb/alert_handler_esc_timer_fpv.sv
+ - tb/alert_handler_esc_timer_tb.sv
file_type: systemVerilogSource
targets:
@@ -22,4 +22,4 @@
default_tool: icarus
filesets:
- files_fpv
- toplevel: alert_handler_esc_timer_fpv
+ toplevel: alert_handler_esc_timer_tb
diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/fpv/alert_handler_ping_timer_fpv.core b/hw/top_earlgrey/ip_autogen/alert_handler/fpv/alert_handler_ping_timer_fpv.core
index 8f7765d..f7a7320 100644
--- a/hw/top_earlgrey/ip_autogen/alert_handler/fpv/alert_handler_ping_timer_fpv.core
+++ b/hw/top_earlgrey/ip_autogen/alert_handler/fpv/alert_handler_ping_timer_fpv.core
@@ -12,7 +12,7 @@
files:
- vip/alert_handler_ping_timer_assert_fpv.sv
- tb/alert_handler_ping_timer_bind_fpv.sv
- - tb/alert_handler_ping_timer_fpv.sv
+ - tb/alert_handler_ping_timer_tb.sv
file_type: systemVerilogSource
targets:
@@ -22,4 +22,4 @@
default_tool: icarus
filesets:
- files_fpv
- toplevel: alert_handler_ping_timer_fpv
+ toplevel: alert_handler_ping_timer_tb
diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/fpv/tb/alert_handler_esc_timer_fpv.sv b/hw/top_earlgrey/ip_autogen/alert_handler/fpv/tb/alert_handler_esc_timer_fpv.sv
deleted file mode 100644
index f1847e5..0000000
--- a/hw/top_earlgrey/ip_autogen/alert_handler/fpv/tb/alert_handler_esc_timer_fpv.sv
+++ /dev/null
@@ -1,49 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
-// Testbench module for alert_handler_esc_timer.
-// Intended to be used with a formal tool.
-
-module alert_handler_esc_timer_fpv import alert_pkg::*; (
- input clk_i,
- input rst_ni,
- input en_i,
- input clr_i,
- input accu_trig_i,
- input accu_fail_i,
- input timeout_en_i,
- input [EscCntDw-1:0] timeout_cyc_i,
- input [N_ESC_SEV-1:0] esc_en_i,
- input [N_ESC_SEV-1:0][PHASE_DW-1:0] esc_map_i,
- input [N_PHASES-1:0][EscCntDw-1:0] phase_cyc_i,
- input [PHASE_DW-1:0] crashdump_phase_i,
- output logic latch_crashdump_o,
- output logic esc_trig_o,
- output logic[EscCntDw-1:0] esc_cnt_o,
- output logic[N_ESC_SEV-1:0] esc_sig_req_o,
- output cstate_e esc_state_o
-);
-
- alert_handler_esc_timer i_alert_handler_esc_timer (
- .clk_i,
- .rst_ni,
- .en_i,
- .clr_i,
- .accu_trig_i,
- .accu_fail_i,
- .timeout_en_i,
- .timeout_cyc_i,
- .esc_en_i,
- .esc_map_i,
- .phase_cyc_i,
- .crashdump_phase_i,
- .latch_crashdump_o,
- .esc_trig_o,
- .esc_cnt_o,
- .esc_sig_req_o,
- .esc_state_o
- );
-
-
-endmodule : alert_handler_esc_timer_fpv
diff --git a/hw/ip_templates/alert_handler/fpv/tb/alert_handler_esc_timer_fpv.sv b/hw/top_earlgrey/ip_autogen/alert_handler/fpv/tb/alert_handler_esc_timer_tb.sv
similarity index 91%
copy from hw/ip_templates/alert_handler/fpv/tb/alert_handler_esc_timer_fpv.sv
copy to hw/top_earlgrey/ip_autogen/alert_handler/fpv/tb/alert_handler_esc_timer_tb.sv
index f1847e5..25b641f 100644
--- a/hw/ip_templates/alert_handler/fpv/tb/alert_handler_esc_timer_fpv.sv
+++ b/hw/top_earlgrey/ip_autogen/alert_handler/fpv/tb/alert_handler_esc_timer_tb.sv
@@ -5,7 +5,7 @@
// Testbench module for alert_handler_esc_timer.
// Intended to be used with a formal tool.
-module alert_handler_esc_timer_fpv import alert_pkg::*; (
+module alert_handler_esc_timer_tb import alert_pkg::*; (
input clk_i,
input rst_ni,
input en_i,
@@ -46,4 +46,4 @@
);
-endmodule : alert_handler_esc_timer_fpv
+endmodule : alert_handler_esc_timer_tb
diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/fpv/tb/alert_handler_ping_timer_fpv.sv b/hw/top_earlgrey/ip_autogen/alert_handler/fpv/tb/alert_handler_ping_timer_fpv.sv
deleted file mode 100644
index ca18a84..0000000
--- a/hw/top_earlgrey/ip_autogen/alert_handler/fpv/tb/alert_handler_ping_timer_fpv.sv
+++ /dev/null
@@ -1,48 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
-// Testbench module for ping timer in alert handler. Intended to use with
-// a formal tool.
-
-module alert_handler_ping_timer_fpv import alert_pkg::*; (
- input clk_i,
- input rst_ni,
- output logic edn_req_o,
- input edn_ack_i,
- input [LfsrWidth-1:0] edn_data_i,
- input en_i,
- input [NAlerts-1:0] alert_ping_en_i,
- input [PING_CNT_DW-1:0] ping_timeout_cyc_i,
- input [PING_CNT_DW-1:0] wait_cyc_mask_i,
- output logic [NAlerts-1:0] alert_ping_req_o,
- output logic [N_ESC_SEV-1:0] esc_ping_req_o,
- input [NAlerts-1:0] alert_ping_ok_i,
- input [N_ESC_SEV-1:0] esc_ping_ok_i,
- output logic alert_ping_fail_o,
- output logic esc_ping_fail_o
-);
-
- alert_handler_ping_timer #(
- // disable max length check in FPV, otherwise this
- // will not converge within acceptable compute time
- .MaxLenSVA ( 1'b0 )
- ) i_alert_handler_ping_timer (
- .clk_i ,
- .rst_ni ,
- .edn_req_o ,
- .edn_ack_i ,
- .edn_data_i ,
- .en_i ,
- .alert_ping_en_i ,
- .ping_timeout_cyc_i,
- .wait_cyc_mask_i ,
- .alert_ping_req_o ,
- .esc_ping_req_o ,
- .alert_ping_ok_i ,
- .esc_ping_ok_i ,
- .alert_ping_fail_o ,
- .esc_ping_fail_o
- );
-
-endmodule : alert_handler_ping_timer_fpv
diff --git a/hw/ip_templates/alert_handler/fpv/tb/alert_handler_ping_timer_fpv.sv b/hw/top_earlgrey/ip_autogen/alert_handler/fpv/tb/alert_handler_ping_timer_tb.sv
similarity index 93%
copy from hw/ip_templates/alert_handler/fpv/tb/alert_handler_ping_timer_fpv.sv
copy to hw/top_earlgrey/ip_autogen/alert_handler/fpv/tb/alert_handler_ping_timer_tb.sv
index ca18a84..2b85385 100644
--- a/hw/ip_templates/alert_handler/fpv/tb/alert_handler_ping_timer_fpv.sv
+++ b/hw/top_earlgrey/ip_autogen/alert_handler/fpv/tb/alert_handler_ping_timer_tb.sv
@@ -5,7 +5,7 @@
// Testbench module for ping timer in alert handler. Intended to use with
// a formal tool.
-module alert_handler_ping_timer_fpv import alert_pkg::*; (
+module alert_handler_ping_timer_tb import alert_pkg::*; (
input clk_i,
input rst_ni,
output logic edn_req_o,
@@ -45,4 +45,4 @@
.esc_ping_fail_o
);
-endmodule : alert_handler_ping_timer_fpv
+endmodule : alert_handler_ping_timer_tb
diff --git a/hw/top_earlgrey/ip_autogen/rv_plic/fpv/rv_plic_fpv.core b/hw/top_earlgrey/ip_autogen/rv_plic/fpv/rv_plic_fpv.core
index 2c57e65..67240cb 100644
--- a/hw/top_earlgrey/ip_autogen/rv_plic/fpv/rv_plic_fpv.core
+++ b/hw/top_earlgrey/ip_autogen/rv_plic/fpv/rv_plic_fpv.core
@@ -14,7 +14,7 @@
- lowrisc:fpv:csr_assert_gen
files:
- tb/rv_plic_bind_fpv.sv
- - tb/rv_plic_fpv.sv
+ - tb/rv_plic_tb.sv
- vip/rv_plic_assert_fpv.sv
file_type: systemVerilogSource
@@ -35,7 +35,7 @@
- files_formal
generate:
- csr_assert_gen
- toplevel: rv_plic_fpv
+ toplevel: rv_plic_tb
formal:
<<: *default_target
diff --git a/hw/top_earlgrey/ip_autogen/rv_plic/fpv/tb/rv_plic_fpv.sv b/hw/top_earlgrey/ip_autogen/rv_plic/fpv/tb/rv_plic_tb.sv
similarity index 95%
rename from hw/top_earlgrey/ip_autogen/rv_plic/fpv/tb/rv_plic_fpv.sv
rename to hw/top_earlgrey/ip_autogen/rv_plic/fpv/tb/rv_plic_tb.sv
index c5b218f..37ebbf1 100644
--- a/hw/top_earlgrey/ip_autogen/rv_plic/fpv/tb/rv_plic_fpv.sv
+++ b/hw/top_earlgrey/ip_autogen/rv_plic/fpv/tb/rv_plic_tb.sv
@@ -4,7 +4,7 @@
//
// Testbench module for rv_plic. Intended to use with a formal tool.
-module rv_plic_fpv import rv_plic_reg_pkg::*; #(
+module rv_plic_tb import rv_plic_reg_pkg::*; #(
// test all implementations
localparam int unsigned NumInstances = 1
) (
@@ -37,4 +37,4 @@
.msip_o (msip_o[0])
);
-endmodule : rv_plic_fpv
+endmodule : rv_plic_tb
