| commit | 42dd028a22f65ddf4710938cb23e429800e2370c | [log] [tgz] |
|---|---|---|
| author | Greg Chadwick <gac@lowrisc.org> | Mon Oct 19 16:43:52 2020 +0100 |
| committer | Greg Chadwick <gac@lowrisc.org> | Thu Oct 29 19:34:22 2020 +0000 |
| tree | d4d735323c32daf86d717798ca889d1d38d30478 | |
| parent | 7285a9896cdc7521c312f0cdddfcee9a5ea9dcf6 [diff] |
[otbn] Add stall on first cycle to ISS. The RTL issues its first instruction fetch the cycle after the start signal is raised. So actual instruction execution does begin until the cycle after that. A stall is added to the first cycle of the ISS execution to match this behaviour. In addition the done signal from OTBN is registered. This is required to ensure it syncs up with the ISS done signal with the new stall on first cycle behaviour and makes more sense than adjusting the ISS to match the previous RTL behaviour as it removes a feedthrough path from the RTL. Signed-off-by: Greg Chadwick <gac@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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