commit 42d032fb55c5d30b1834b3fe744c8584fedaba11
author Srikrishna Iyer <sriyer@google.com> Wed Mar 04 23:55:44 2020 -0800
committer sriyerg <46467186+sriyerg@users.noreply.github.com> Thu Mar 05 12:27:56 2020 -0800
tree f54e58bad6ec117317bb76fa5f25debf34790139
parent 3e9d888815f2469b87e2a4f6c5835df41f782ca8

[top_earlgrey dv] Enabled DV with dvsim

- Tool updates to enable sw build using meson wihin dvsim
- SW based tests now passing at chip level
- Added chip_sim_cfg.hjson to the top_earlgrey sim cfgs set so that chip
level DV tests get run as a part of nightly and CI

Signed-off-by: Srikrishna Iyer <sriyer@google.com>

util/dvsim/Deploy.py

diff --git a/util/dvsim/Deploy.py b/util/dvsim/Deploy.py
index 95a4230..adb21d3 100644
--- a/util/dvsim/Deploy.py
+++ b/util/dvsim/Deploy.py
@@ -472,11 +472,14 @@
         self.fail_patterns = []
 
         self.mandatory_cmd_attrs = {
+            "proj_root": False,
             "uvm_test": False,
             "uvm_test_seq": False,
             "run_opts": False,
             "sw_dir": False,
             "sw_name": False,
+            "sw_build_device":False,
+            "sw_build_dir":False,
             "run_dir": False,
             "run_cmd": False,
             "run_opts": False