| commit | 9b99f610942abe15678e95690dfac29e6494a47a | [log] [tgz] |
|---|---|---|
| author | Dan McArdle <dmcardle@google.com> | Wed Sep 07 14:39:19 2022 -0400 |
| committer | Alphan Ulusoy <alphan@google.com> | Thu Sep 22 05:12:01 2022 -0400 |
| tree | f6c288f9e05ba2d00ccce3bfeccab8360f00abc2 | |
| parent | ea4c96d37c8edd46daa9558bc1b7bc10e624f9ae [diff] |
[bazel] Use ROM in SRAM program test instead of Test ROM
Prior to this commit, we relied on the startup routine in the Test ROM
that configures the PMP to enable RWX the entire SRAM region. The ROM
does not have the same "gadget" for us to reuse, so we needed to figure
out how to do the same thing with OpenOCD commands. This proved very
tricky due to implementation details of OpenTitan's debug module[^0],
but we did find a workaround.
The test is a little flaky now that we're using the ROM. I think there
are at least two sources of flakiness: (1) the ROM bootloops because it
cannot find ROM_EXT in either flash slot, and (2) the watchdog timer.
* I think that establishing the OpenOCD connection races with the
device rebooting, so if we're unlucky the connection will fail. If
this is the case, we may be able to automatically retry OpenOCD
until the connection succeeds.
* I've addressed the timer issue by adding a sequence of GDB commands
that disable the watchdog timer.
While trying to reduce flakiness, it's easy to succumb to confirmation
bias. To smooth out the noise a bit, I've been repeating the test 20
times with the command below. Anecdotally, I'm seeing somewhere between
0 and 7 flakes per 20 runs.
./bazelisk.sh test --runs_per_test=20 \
--cache_test_results=no --test_output=streamed \
//sw/device/examples/sram_program:sram_program_fpga_cw310_test
[^0]: https://github.com/lowRISC/opentitan/issues/14978
Fixes #13968
Signed-off-by: Dan McArdle <dmcardle@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
This repository contains hardware, software and utilities written as part of the OpenTitan project. It is structured as monolithic repository, or “monorepo”, where all components live in one repository. It exists to enable collaboration across partners participating in the OpenTitan project.
The project contains comprehensive documentation of all IPs and tools. You can access it online at docs.opentitan.org.
Have a look at CONTRIBUTING and our documentation on project organization and processes for guidelines on how to contribute code to this repository.
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).