[flash_ctrl] update cm label for bus integrity clarity
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.hjson b/hw/ip/flash_ctrl/data/flash_ctrl.hjson
index 3037509..9307593 100644
--- a/hw/ip/flash_ctrl/data/flash_ctrl.hjson
+++ b/hw/ip/flash_ctrl/data/flash_ctrl.hjson
@@ -192,7 +192,25 @@
],
countermeasures: [
- { name: "BUS.INTEGRITY",
+ { name: "REG.BUS.INTEGRITY",
+ desc: '''
+ End-to-end bus integrity scheme.
+ Since there are multiple access points for flash, please see
+ Transmission Integrity Faults in the documentation for more details.
+
+ The bus integrity scheme for flash is different from other comportable modules.
+ '''
+ }
+ { name: "HOST.BUS.INTEGRITY",
+ desc: '''
+ End-to-end bus integrity scheme.
+ Since there are multiple access points for flash, please see
+ Transmission Integrity Faults in the documentation for more details.
+
+ The bus integrity scheme for flash is different from other comportable modules.
+ '''
+ }
+ { name: "MEM.BUS.INTEGRITY",
desc: '''
End-to-end bus integrity scheme.
Since there are multiple access points for flash, please see
diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.hjson.tpl b/hw/ip/flash_ctrl/data/flash_ctrl.hjson.tpl
index b4ce2c5..20786a8 100644
--- a/hw/ip/flash_ctrl/data/flash_ctrl.hjson.tpl
+++ b/hw/ip/flash_ctrl/data/flash_ctrl.hjson.tpl
@@ -203,7 +203,25 @@
],
countermeasures: [
- { name: "BUS.INTEGRITY",
+ { name: "REG.BUS.INTEGRITY",
+ desc: '''
+ End-to-end bus integrity scheme.
+ Since there are multiple access points for flash, please see
+ Transmission Integrity Faults in the documentation for more details.
+
+ The bus integrity scheme for flash is different from other comportable modules.
+ '''
+ }
+ { name: "HOST.BUS.INTEGRITY",
+ desc: '''
+ End-to-end bus integrity scheme.
+ Since there are multiple access points for flash, please see
+ Transmission Integrity Faults in the documentation for more details.
+
+ The bus integrity scheme for flash is different from other comportable modules.
+ '''
+ }
+ { name: "MEM.BUS.INTEGRITY",
desc: '''
End-to-end bus integrity scheme.
Since there are multiple access points for flash, please see
diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl b/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl
index fc53fa1..bb52f60 100644
--- a/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl
+++ b/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl
@@ -112,7 +112,7 @@
logic intg_err;
logic eflash_cmd_intg_err;
- // SEC_CM: BUS.INTEGRITY
+ // SEC_CM: REG.BUS.INTEGRITY
// SEC_CM: CTRL.CONFIG.REGWEN
// SEC_CM: DATA_REGIONS.CONFIG.REGWEN, DATA_REGIONS.CONFIG.SHADOW
// SEC_CM: INFO_REGIONS.CONFIG.REGWEN, INFO_REGIONS.CONFIG.SHADOW
@@ -1230,6 +1230,7 @@
.lc_en_i(host_enable)
);
+ // SEC_CM: HOST.BUS.INTEGRITY
tlul_adapter_sram #(
.SramAw(BusAddrW),
.SramDw(BusWidth),
diff --git a/hw/ip/flash_ctrl/data/flash_ctrl_sec_cm_testplan.hjson b/hw/ip/flash_ctrl/data/flash_ctrl_sec_cm_testplan.hjson
index e15a643..9b7a279 100644
--- a/hw/ip/flash_ctrl/data/flash_ctrl_sec_cm_testplan.hjson
+++ b/hw/ip/flash_ctrl/data/flash_ctrl_sec_cm_testplan.hjson
@@ -24,8 +24,20 @@
{
testpoints: [
{
- name: sec_cm_bus_integrity
- desc: "Verify the countermeasure(s) BUS.INTEGRITY."
+ name: sec_cm_reg_bus_integrity
+ desc: "Verify the countermeasure(s) REG.BUS.INTEGRITY."
+ milestone: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_host_bus_integrity
+ desc: "Verify the countermeasure(s) HOST.BUS.INTEGRITY."
+ milestone: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_mem_bus_integrity
+ desc: "Verify the countermeasure(s) MEM.BUS.INTEGRITY."
milestone: V2S
tests: []
}
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
index f3867ef..ba9a06b 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
@@ -112,7 +112,7 @@
logic intg_err;
logic eflash_cmd_intg_err;
- // SEC_CM: BUS.INTEGRITY
+ // SEC_CM: REG.BUS.INTEGRITY
// SEC_CM: CTRL.CONFIG.REGWEN
// SEC_CM: DATA_REGIONS.CONFIG.REGWEN, DATA_REGIONS.CONFIG.SHADOW
// SEC_CM: INFO_REGIONS.CONFIG.REGWEN, INFO_REGIONS.CONFIG.SHADOW
@@ -1231,6 +1231,7 @@
.lc_en_i(host_enable)
);
+ // SEC_CM: HOST.BUS.INTEGRITY
tlul_adapter_sram #(
.SramAw(BusAddrW),
.SramDw(BusWidth),
diff --git a/hw/ip/flash_ctrl/rtl/flash_phy_prog.sv b/hw/ip/flash_ctrl/rtl/flash_phy_prog.sv
index 73e5ea6..31d7b59 100644
--- a/hw/ip/flash_ctrl/rtl/flash_phy_prog.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_phy_prog.sv
@@ -114,6 +114,7 @@
logic data_err;
// use the tlul integrity module directly for bus integrity
+ // SEC_CM: MEM.BUS.INTEGRITY
tlul_data_integ_dec u_data_intg_chk (
.data_intg_i(data_i),
.data_err_o(data_err)
diff --git a/hw/ip/flash_ctrl/rtl/flash_phy_rd.sv b/hw/ip/flash_ctrl/rtl/flash_phy_rd.sv
index bf081fd..9b8f575 100644
--- a/hw/ip/flash_ctrl/rtl/flash_phy_rd.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_phy_rd.sv
@@ -588,6 +588,7 @@
end
// use the tlul integrity module directly for bus integrity
+ // SEC_CM: MEM.BUS.INTEGRITY
tlul_data_integ_enc u_bus_intg (
.data_i(data_out_pre),
.data_intg_o(data_o)
diff --git a/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson b/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson
index 419fc35..f216ab5 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson
+++ b/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson
@@ -198,7 +198,25 @@
],
countermeasures: [
- { name: "BUS.INTEGRITY",
+ { name: "REG.BUS.INTEGRITY",
+ desc: '''
+ End-to-end bus integrity scheme.
+ Since there are multiple access points for flash, please see
+ Transmission Integrity Faults in the documentation for more details.
+
+ The bus integrity scheme for flash is different from other comportable modules.
+ '''
+ }
+ { name: "HOST.BUS.INTEGRITY",
+ desc: '''
+ End-to-end bus integrity scheme.
+ Since there are multiple access points for flash, please see
+ Transmission Integrity Faults in the documentation for more details.
+
+ The bus integrity scheme for flash is different from other comportable modules.
+ '''
+ }
+ { name: "MEM.BUS.INTEGRITY",
desc: '''
End-to-end bus integrity scheme.
Since there are multiple access points for flash, please see
diff --git a/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl_sec_cm_testplan.hjson b/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl_sec_cm_testplan.hjson
index e15a643..9b7a279 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl_sec_cm_testplan.hjson
+++ b/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl_sec_cm_testplan.hjson
@@ -24,8 +24,20 @@
{
testpoints: [
{
- name: sec_cm_bus_integrity
- desc: "Verify the countermeasure(s) BUS.INTEGRITY."
+ name: sec_cm_reg_bus_integrity
+ desc: "Verify the countermeasure(s) REG.BUS.INTEGRITY."
+ milestone: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_host_bus_integrity
+ desc: "Verify the countermeasure(s) HOST.BUS.INTEGRITY."
+ milestone: V2S
+ tests: []
+ }
+ {
+ name: sec_cm_mem_bus_integrity
+ desc: "Verify the countermeasure(s) MEM.BUS.INTEGRITY."
milestone: V2S
tests: []
}
diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
index 598ecdd..87b19d0 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
@@ -118,7 +118,7 @@
logic intg_err;
logic eflash_cmd_intg_err;
- // SEC_CM: BUS.INTEGRITY
+ // SEC_CM: REG.BUS.INTEGRITY
// SEC_CM: CTRL.CONFIG.REGWEN
// SEC_CM: DATA_REGIONS.CONFIG.REGWEN, DATA_REGIONS.CONFIG.SHADOW
// SEC_CM: INFO_REGIONS.CONFIG.REGWEN, INFO_REGIONS.CONFIG.SHADOW
@@ -1237,6 +1237,7 @@
.lc_en_i(host_enable)
);
+ // SEC_CM: HOST.BUS.INTEGRITY
tlul_adapter_sram #(
.SramAw(BusAddrW),
.SramDw(BusWidth),
