| commit | 417e264c10b2615a33d3ffc81e79219f20ad5523 | [log] [tgz] |
|---|---|---|
| author | Cindy Chen <chencindy@opentitan.org> | Tue Aug 17 15:41:14 2021 -0700 |
| committer | cindychip <cindy.chen0316@gmail.com> | Tue Aug 17 21:04:44 2021 -0700 |
| tree | 49c2c400754fc1a6be25fe72acb5123bbe5d177e | |
| parent | 6e1480a07eb87bfa17b14615170eff7fe6cde4eb [diff] |
[dv/prim_esc] Fix prim_esc regression error Due to testbench clock and dricing issue, waiting one clock cycle is not enough to finish the escalation request and start ping request. So we wait at least two clock cycles. Signed-off-by: Cindy Chen <chencindy@opentitan.org>
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