[uart] Reaching D3/V3 stage
After helding the signoff meeting (2019-10-28), the UART IP now reached
D3/V3 stage at 2019-11-01. Checklist document and project Hjson are
updated accordingly.
Co-authored-by: Weicai Yang <weicai@google.com>
diff --git a/doc/project/ip_checklist.md.tpl b/doc/project/ip_checklist.md.tpl
index 3d906af..6cd9a53 100644
--- a/doc/project/ip_checklist.md.tpl
+++ b/doc/project/ip_checklist.md.tpl
@@ -20,8 +20,6 @@
RTL | [FUNC_IMPLEMENTED][] | Not Started |
RTL | [ASSERT_KNOWN_ADDED][]| Not Started |
Code Quality | [LINT_SETUP][] | Not Started |
- | | |
-Review | [D1_REVIEWED][] | Not Started |
Review | Reviewer(s) | Not Started |
Review | Signoff date | Not Started |
@@ -56,8 +54,6 @@
Code Quality | [CDC_SETUP][] | Not Started |
Code Quality | [FPGA_TIMING][] | Not Started |
Code Quality | [CDC_SYNCMACRO][] | Not Started |
- | | |
-Review | [D2_REVIEWED][] | Not Started |
Review | Reviewer(s) | Not Started |
Review | Signoff date | Not Started |
@@ -94,8 +90,6 @@
Review | [REVIEW_SW_FATAL_ERR][] | Not Started |
Review | [REVIEW_SW_CHANGE][] | Not Started |
Review | [REVIEW_SW_ERRATA][] | Not Started |
- | | |
-Review | [D3_REVIEWED][] | Not Started |
Review | Reviewer(s) | Not Started |
Review | Signoff date | Not Started |
diff --git a/doc/rm/checklist.md b/doc/rm/checklist.md
index 4d7d92c..18a7cd2 100644
--- a/doc/rm/checklist.md
+++ b/doc/rm/checklist.md
@@ -47,10 +47,6 @@
Lint run setup, compiles and runs. It is acceptable to have lint errors and
warnings at this stage.
-### D1_REVIEWED
-
-D1 checklist reviewed, and signed off. Exception rationales documented.
-
## D2
### NEW_FEATURES
@@ -119,10 +115,6 @@
CDC Sync flops use behavioral synchronization macros(`prim_flop_2sync`) not
2flops.
-### D2_REVIEWED
-
-D2 checklist reviewed, and signed off. Exception rationales documented
-
## D3
### NEW_FEATURES_D3
@@ -165,10 +157,6 @@
Review Design Change with SW: Review known "Won't Fix" bugs and "Errata".
-### D3_REVIEWED
-
-D3 checklist reviewed, and signed off. Exception rationales documented.
-
## V1
For a transition from V0 to V1, the following items are expected be completed.
@@ -191,7 +179,6 @@
### PRELIMINARY_ASSERTION_CHECKS_ADDED
- All available interface assertion monitors hooked up (example: tlul_assert)
-- All DUT outputs have X / unknown checks when out of reset
### TB_ENV_CREATED
@@ -334,6 +321,9 @@
Ensure that the complete testbench code is free from TODOs.
+### X_PROP_ANALYSIS_COMPLETED
+
+X Propagation Analysis complete
### NIGHTLY_REGRESSION_AT_100
diff --git a/hw/ip/uart/data/uart.prj.hjson b/hw/ip/uart/data/uart.prj.hjson
index efc75a5..3050f5e 100644
--- a/hw/ip/uart/data/uart.prj.hjson
+++ b/hw/ip/uart/data/uart.prj.hjson
@@ -5,7 +5,8 @@
{
name: "uart",
version: "1.0",
- life_stage: "L1",
- design_stage: "D0",
- verification_stage: "V0",
+ life_stage: "L2",
+ design_stage: "D3",
+ verification_stage: "V3",
+ notes: "signoff commit id: 92e4298f8c2de268b2420a2c16939cd0784f1bf8"
}
diff --git a/hw/ip/uart/doc/checklist.md b/hw/ip/uart/doc/checklist.md
new file mode 100644
index 0000000..67a56db
--- /dev/null
+++ b/hw/ip/uart/doc/checklist.md
@@ -0,0 +1,220 @@
+---
+title: "UART Checklist"
+---
+
+This checklist is for [Hardware Stage][] transitions for the [UART peripheral.](../)
+All checklist items refer to the content in the [Checklist.]({{<relref "/doc/rm/checklist.md">}})
+
+[Hardware Stage]: {{<relref "/doc/ug/hw_stages.md" >}}
+
+
+## Design Checklist
+
+### D1
+
+Type | Item | Resolution | Note/Collaterals
+--------------|-----------------------|-------------|------------------
+Documentation | [SPEC_COMPLETE][] | Done | [UART Spec](../)
+Documentation | [CSR_DEFINED][] | Done |
+RTL | [CLKRST_CONNECTED][] | Done |
+RTL | [IP_TOP][] | Done |
+RTL | [IP_INSTANCED][] | Done |
+RTL | [MEM_INSTANCED_80][] | N/A |
+RTL | [FUNC_IMPLEMENTED][] | Done |
+RTL | [ASSERT_KNOWN_ADDED][]| Done |
+Code Quality | [LINT_SETUP][] | Done |
+Review | Reviewer(s) | Done | @weicaiyang @sjgitty
+Review | Signoff date | Done | 2019-10-28
+
+
+[SPEC_COMPLETE]: {{<relref "/doc/rm/checklist.md#spec-complete" >}}
+[CSR_DEFINED]: {{<relref "/doc/rm/checklist.md#csr-defined" >}}
+[CLKRST_CONNECTED]: {{<relref "/doc/rm/checklist.md#clkrst-connected" >}}
+[IP_TOP]: {{<relref "/doc/rm/checklist.md#ip-top" >}}
+[IP_INSTANCED]: {{<relref "/doc/rm/checklist.md#ip-instanced" >}}
+[MEM_INSTANCED_80]: {{<relref "/doc/rm/checklist.md#mem-instanced-80" >}}
+[FUNC_IMPLEMENTED]: {{<relref "/doc/rm/checklist.md#func-implemented" >}}
+[ASSERT_KNOWN_ADDED]: {{<relref "/doc/rm/checklist.md#assert-known-added" >}}
+[LINT_SETUP]: {{<relref "/doc/rm/checklist.md#lint-setup" >}}
+
+### D1 Exceptions
+
+[MEM_INSTANCED_80][] is waived as UART doesn't have memories inside.
+
+### D2
+
+Type | Item | Resolution | Note/Collaterals
+--------------|-------------------------|-------------|------------------
+Documentation | [NEW_FEATURES][] | N/A |
+Documentation | [BLOCK_DIAGRAM][] | N/A |
+Documentation | [DOC_INTERFACE][] | Done |
+Documentation | [MISSING_FUNC][] | N/A |
+Documentation | [FEATURE_FROZEN][] | Done |
+RTL | [FEATURE_COMPLETE][] | Done |
+RTL | [AREA_SANITY_CHECK][] | Done | Area Sanity Check Done (on FPGA)
+RTL | [PORT_FROZEN][] | Done |
+RTL | [ARCHITECTURE_FROZEN][] | Done |
+RTL | [REVIEW_TODO][] | Done |
+RTL | [STYLE_X][] | N/A | No assignment of X
+Code Quality | [LINT_PASS][] | Done | Lint waivers reviewed
+Code Quality | [CDC_SETUP][] | N/A | No CDC path
+Code Quality | [FPGA_TIMING][] | Done | Fmax 50MHz on NexysVideo
+Code Quality | [CDC_SYNCMACRO][] | N/A |
+Review | Reviewer(s) | Done | @msfschaffner @weicaiyang @sriyerg @sjgitty
+Review | Signoff date | Done | 2019-10-28
+
+[NEW_FEATURES]: {{<relref "/doc/rm/checklist.md#new-features" >}}
+[BLOCK_DIAGRAM]: {{<relref "/doc/rm/checklist.md#block-diagram" >}}
+[DOC_INTERFACE]: {{<relref "/doc/rm/checklist.md#doc-interface" >}}
+[MISSING_FUNC]: {{<relref "/doc/rm/checklist.md#missing-func" >}}
+[FEATURE_FROZEN]: {{<relref "/doc/rm/checklist.md#feature-frozen" >}}
+[FEATURE_COMPLETE]: {{<relref "/doc/rm/checklist.md#feature-complete" >}}
+[AREA_SANITY_CHECK]: {{<relref "/doc/rm/checklist.md#area-sanity-check" >}}
+[DEBUG_BUS]: {{<relref "/doc/rm/checklist.md#debug-bus" >}}
+[PORT_FROZEN]: {{<relref "/doc/rm/checklist.md#port-frozen" >}}
+[ARCHITECTURE_FROZEN]: {{<relref "/doc/rm/checklist.md#architecture-frozen" >}}
+[REVIEW_TODO]: {{<relref "/doc/rm/checklist.md#review-todo" >}}
+[STYLE_X]: {{<relref "/doc/rm/checklist.md#style-x" >}}
+[STYLE_LINT_SETUP]: {{<relref "/doc/rm/checklist.md#style-lint-setup" >}}
+[LINT_PASS]: {{<relref "/doc/rm/checklist.md#lint-pass" >}}
+[CDC_SETUP]: {{<relref "/doc/rm/checklist.md#cdc-setup" >}}
+[CDC_SYNCMACRO]: {{<relref "/doc/rm/checklist.md#cdc-syncmacro" >}}
+[FPGA_TIMING]: {{<relref "/doc/rm/checklist.md#fpga-timing" >}}
+
+### D3
+
+ Type | Item | Resolution | Note/Collaterals
+--------------|-------------------------|-------------|------------------
+Documentation | [NEW_FEATURES_D3][] | N/A |
+RTL | [TODO_COMPLETE][] | Done |
+Code Quality | [LINT_COMPLETE][] | Done |
+Code Quality | [CDC_COMPLETE][] | N/A |
+Review | [REVIEW_RTL][] | Done | by @msfschaffner
+Review | [REVIEW_DELETED_FF][] | N/A | Not reported by FPGA (@eunchan double-check)
+Review | [REVIEW_SW_CSR][] | Done |
+Review | [REVIEW_SW_FATAL_ERR][] | Done | by @moidx
+Review | [REVIEW_SW_CHANGE][] | N/A |
+Review | [REVIEW_SW_ERRATA][] | Done |
+Review | Reviewer(s) | Done | @weicaiyang @sjgitty @msfschaffner
+Review | Signoff date | Done | 2019-10-31
+
+[NEW_FEATURES_D3]: {{<relref "/doc/rm/checklist.md#new-features-d3" >}}
+[TODO_COMPLETE]: {{<relref "/doc/rm/checklist.md#todo-complete" >}}
+[LINT_COMPLETE]: {{<relref "/doc/rm/checklist.md#lint-complete" >}}
+[CDC_COMPLETE]: {{<relref "/doc/rm/checklist.md#cdc-complete" >}}
+[REVIEW_RTL]: {{<relref "/doc/rm/checklist.md#review-rtl" >}}
+[REVIEW_DBG]: {{<relref "/doc/rm/checklist.md#review-dbg" >}}
+[REVIEW_DELETED_FF]: {{<relref "/doc/rm/checklist.md#review-deleted-ff" >}}
+[REVIEW_SW_CSR]: {{<relref "/doc/rm/checklist.md#review-sw-csr" >}}
+[REVIEW_SW_FATAL_ERR]: {{<relref "/doc/rm/checklist.md#review-sw-fatal-err" >}}
+[REVIEW_SW_CHANGE]: {{<relref "/doc/rm/checklist.md#review-sw-change" >}}
+[REVIEW_SW_ERRATA]: {{<relref "/doc/rm/checklist.md#review-sw-errata" >}}
+
+## Verification Checklist
+
+### Checklists for milestone V1
+ Type | Item | Resolution | Note/Collaterals
+--------------|---------------------------------------|-------------|------------------
+Documentation | [DV_PLAN_DRAFT_COMPLETED][] | Done | [uart_dv_plan]({{<relref "dv_plan/" >}})
+Documentation | [TESTPLAN_COMPLETED][] | Done |
+Testbench | [TB_TOP_CREATED][] | Done |
+Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done |
+Testbench | [TB_ENV_CREATED][] | Done |
+Testbench | [RAL_MODEL_GEN_AUTOMATED][] | Done |
+Testbench | [TB_GEN_AUTOMATED][] | N/A |
+Tests | [SANITY_TEST_PASSING][] | Done |
+Tests | [CSR_MEM_TEST_SUITE_PASSING][] | Done |
+Tool Setup | [ALT_TOOL_SETUP][] | Done |
+Regression | [SANITY_REGRESSION_SETUP][] | Done | Exception (implemented in local)
+Regression | [NIGHTLY_REGRESSION_SETUP][] | Done | Exception (implemented in local)
+Coverage | [COVERAGE_MODEL_ADDED][] | Done |
+Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | N/A | Except for IP module
+Review | [DESIGN_SPEC_REVIEWED][] | Done |
+Review | [DV_PLAN_TESTPLAN_REVIEWED][] | Done |
+Review | [STD_TEST_CATEGORIES_PLANNED][] | Done | Exception (Security, Power, Debug)
+Review | [V2_CHECKLIST_SCOPED][] | Done |
+Review | Reviewer(s) | Done | @eunchan @sjgitty @sriyerg
+Review | Signoff date | Done | 2019-10-28
+
+
+[DV_PLAN_DRAFT_COMPLETED]: {{<relref "/doc/rm/checklist.md#dv-plan-draft-completed" >}}
+[TESTPLAN_COMPLETED]: {{<relref "/doc/rm/checklist.md#testplan-completed" >}}
+[TB_TOP_CREATED]: {{<relref "/doc/rm/checklist.md#tb-top-created" >}}
+[PRELIMINARY_ASSERTION_CHECKS_ADDED]: {{<relref "/doc/rm/checklist.md#preliminary-assertion-checks-added" >}}
+[TB_ENV_CREATED]: {{<relref "/doc/rm/checklist.md#tb-env-created" >}}
+[RAL_MODEL_GEN_AUTOMATED]: {{<relref "/doc/rm/checklist.md#ral-model-gen-automated" >}}
+[TB_GEN_AUTOMATED]: {{<relref "/doc/rm/checklist.md#tb-gen-automated" >}}
+[SANITY_TEST_PASSING]: {{<relref "/doc/rm/checklist.md#sanity-test-passing" >}}
+[CSR_MEM_TEST_SUITE_PASSING]: {{<relref "/doc/rm/checklist.md#csr-mem-test-suite-passing" >}}
+[ALT_TOOL_SETUP]: {{<relref "/doc/rm/checklist.md#alt-tool-setup" >}}
+[SANITY_REGRESSION_SETUP]: {{<relref "/doc/rm/checklist.md#sanity-regression-setup" >}}
+[NIGHTLY_REGRESSION_SETUP]: {{<relref "/doc/rm/checklist.md#nightly-regression-setup" >}}
+[COVERAGE_MODEL_ADDED]: {{<relref "/doc/rm/checklist.md#coverage-model-added" >}}
+[PRE_VERIFIED_SUB_MODULES_V1]: {{<relref "/doc/rm/checklist.md#pre-verified-sub-modules-v1" >}}
+[DESIGN_SPEC_REVIEWED]: {{<relref "/doc/rm/checklist.md#design-spec-reviewed" >}}
+[DV_PLAN_TESTPLAN_REVIEWED]: {{<relref "/doc/rm/checklist.md#dv-plan-testplan-reviewed" >}}
+[STD_TEST_CATEGORIES_PLANNED]: {{<relref "/doc/rm/checklist.md#std-test-categories-planned" >}}
+[V2_CHECKLIST_SCOPED]: {{<relref "/doc/rm/checklist.md#v2-checklist-scoped" >}}
+
+### Checklists for milestone V2
+ Type | Item | Resolution | Note/Collaterals
+--------------|-----------------------------------------|-------------|------------------
+Documentation | [DESIGN_DELTAS_CAPTURED][] | N/A |
+Documentation | [DV_PLAN_COMPLETED][] | Done |
+Testbench | [ALL_INTERFACES_EXERCISED][] | Done |
+Testbench | [ALL_ASSERTION_CHECKS_ADDED][] | Done |
+Testbench | [TB_ENV_COMPLETED][] | Done |
+Tests | [ALL_TESTS_PASSING][] | Done |
+Tests | [FW_SIMULATED][] | N/A |
+Regression | [NIGHTLY_REGRESSION_V2][] | Done |
+Coverage | [CODE_COVERAGE_V2][] | Done |
+Coverage | [FUNCTIONAL_COVERAGE_V2][] | Done |
+Issues | [NO_HIGH_PRIORITY_ISSUES_PENDING][] | Done |
+Issues | [ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED][] | Done |
+Integration | [PRE_VERIFIED_SUB_MODULES_V2][] | N/A |
+Review | [V3_CHECKLIST_SCOPED][] | Done |
+Review | Reviewer(s) | Done | @eunchan @sjgitty @sriyerg
+Review | Signoff date | Done | 2019-10-28
+
+
+[DESIGN_DELTAS_CAPTURED]: {{<relref "/doc/rm/checklist.md#design-deltas-captured" >}}
+[DV_PLAN_COMPLETED]: {{<relref "/doc/rm/checklist.md#dv-plan-completed" >}}
+[ALL_INTERFACES_EXERCISED]: {{<relref "/doc/rm/checklist.md#all-interfaces-exercised" >}}
+[ALL_ASSERTION_CHECKS_ADDED]: {{<relref "/doc/rm/checklist.md#all-assertion-checks-added" >}}
+[TB_ENV_COMPLETED]: {{<relref "/doc/rm/checklist.md#tb-env-completed" >}}
+[ALL_TESTS_PASSING]: {{<relref "/doc/rm/checklist.md#all-tests-passing" >}}
+[FW_SIMULATED]: {{<relref "/doc/rm/checklist.md#fw-simulated" >}}
+[NIGHTLY_REGRESSION_V2]: {{<relref "/doc/rm/checklist.md#nightly-regression-v2" >}}
+[CODE_COVERAGE_V2]: {{<relref "/doc/rm/checklist.md#code-coverage-v2" >}}
+[FUNCTIONAL_COVERAGE_V2]: {{<relref "/doc/rm/checklist.md#functional-coverage-v2" >}}
+[NO_HIGH_PRIORITY_ISSUES_PENDING]: {{<relref "/doc/rm/checklist.md#no-high-priority-issues-pending" >}}
+[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:{{<relref "/doc/rm/checklist.md#all-low-priority-issues-root-caused" >}}
+[PRE_VERIFIED_SUB_MODULES_V2]: {{<relref "/doc/rm/checklist.md#pre-verified-sub-modules-v2" >}}
+[V3_CHECKLIST_SCOPED]: {{<relref "/doc/rm/checklist.md#v3-checklist-scoped" >}}
+
+### Checklists for milestone V3
+ Type | Item | Resolution | Note/Collaterals
+--------------|-----------------------------------|-------------|------------------
+Documentation | [DESIGN_DELTAS_CAPTURED_IF_ANY][] | N/A |
+Testbench | [ALL_TODOS_RESOLVED][] | Done |
+Tests | [X_PROP_ANALYSIS_COMPLETED][] | Waived | Revisit later. Tool setup in progress
+Regression | [NIGHTLY_REGRESSION_AT_100][] | Done |
+Coverage | [CODE_COVERAGE_AT_100][] | Done |[common_cov_excl.el][], [uart_cov_excl.el][]
+Coverage | [FUNCTIONAL_COVERAGE_AT_100][] | Done |
+Issues | [NO_ISSUES_PENDING][] | Done |
+Code Quality | [NO_TOOL_WARNINGS_THROWN][] | Done |
+Integration | [PRE_VERIFIED_SUB_MODULES_V3][] | N/A |
+Review | Reviewer(s) | Done | @eunchan @sjgitty @sriyerg
+Review | Signoff date | Done | 2019-11-01
+
+[DESIGN_DELTAS_CAPTURED_IF_ANY]:{{<relref "/doc/rm/checklist.md#design-deltas-captured-if-any" >}}
+[ALL_TODOS_RESOLVED]: {{<relref "/doc/rm/checklist.md#all-todos-resolved" >}}
+[X_PROP_ANALYSIS_COMPLETED]: {{<relref "/doc/rm/checklist.md#x-prop-analysis-completed" >}}
+[NIGHTLY_REGRESSION_AT_100]: {{<relref "/doc/rm/checklist.md#nightly-regression-at-100" >}}
+[CODE_COVERAGE_AT_100]: {{<relref "/doc/rm/checklist.md#code-coverage-at-100" >}}
+[FUNCTIONAL_COVERAGE_AT_100]: {{<relref "/doc/rm/checklist.md#functional-coverage-at-100" >}}
+[NO_ISSUES_PENDING]: {{<relref "/doc/rm/checklist.md#no-issues-pending" >}}
+[NO_TOOL_WARNINGS_THROWN]: {{<relref "/doc/rm/checklist.md#no-tool-warnings-thrown" >}}
+[PRE_VERIFIED_SUB_MODULES_V3]: {{<relref "/doc/rm/checklist.md#pre-verified-sub-modules-v3" >}}
+[common_cov_excl.el]:https://github.com/lowRISC/opentitan/blob/master/hw/dv/tools/vcs/common_cov_excl.el
+[uart_cov_excl.el]: https://github.com/lowRISC/opentitan/blob/04bb36e0ae1430262b048d400102b0fed43377ac/hw/ip/uart/dv/cov/uart_cov_excl.el
