[flash_ctrl] Fix width mismatch
CntWidth is defined as $clog2(ArbCnt + 1), so this slice is safe.
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
diff --git a/hw/ip/flash_ctrl/rtl/flash_phy_core.sv b/hw/ip/flash_ctrl/rtl/flash_phy_core.sv
index 148ef86..5356379 100644
--- a/hw/ip/flash_ctrl/rtl/flash_phy_core.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_phy_core.sv
@@ -10,7 +10,7 @@
// Most of the items are TODO, at the moment only arbitration logic exists.
module flash_phy_core import flash_phy_pkg::*; #(
- parameter int ArbCnt = 4
+ parameter int unsigned ArbCnt = 4
) (
input clk_i,
input rst_ni,
@@ -118,7 +118,7 @@
logic op_ack;
logic [DataWidth-1:0] scramble_mask;
- assign host_req_masked = host_req_i & (arb_cnt < ArbCnt);
+ assign host_req_masked = host_req_i & (arb_cnt < ArbCnt[CntWidth-1:0]);
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
