| commit | 9cc70b8f98fbac0ae61254463ab4d19cff982d70 | [log] [tgz] |
|---|---|---|
| author | Prajwala Puttappa <prajwalaputtappa@lowrisc.org> | Fri May 27 15:37:24 2022 +0100 |
| committer | weicaiyang <49293026+weicaiyang@users.noreply.github.com> | Mon Jun 20 21:37:42 2022 -0700 |
| tree | b5eae848d0fc4c7c42024a34053d5ca1de52099b | |
| parent | f4ca836484b51ab398b67bbe0294bc9493fb66f5 [diff] |
[otbn, dv] Fixed regression issue in otbn_illegal_mem_acc This commit disables compare check that happens in the memory model whenever an illegal access is done to the imem / dmem while the otbn is busy executing instructions. it also disables end address check inside run_otbn task. Signed-off-by: Prajwala Puttappa <prajwalaputtappa@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
This repository contains hardware, software and utilities written as part of the OpenTitan project. It is structured as monolithic repository, or “monorepo”, where all components live in one repository. It exists to enable collaboration across partners participating in the OpenTitan project.
The project contains comprehensive documentation of all IPs and tools. You can access it online at docs.opentitan.org.
Have a look at [CONTRIBUTING]({{< relref “CONTRIBUTING.md” >}}) and our documentation on project organization and processes for guidelines on how to contribute code to this repository.
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).