commit 3f0e539537087518ef8f7ae94fb8736b71544a98
author Miguel Osorio <miguelosorio@google.com> Thu Jun 09 09:26:53 2022 -0700
committer moidx <migue48@gmail.com> Thu Jun 09 12:20:37 2022 -0700
tree 410be85e8873425ca741d0e3cd22037966824e9d
parent 02b2c0a6067cc654457be84ec5faa6ea8e8bdcbc

[bazel] Skip verilator_options if not available

Fixes issue with FPGA bitstream build rule not having verilator_options
defined.

Signed-off-by: Miguel Osorio <miguelosorio@google.com>

rules/fusesoc.bzl

diff --git a/rules/fusesoc.bzl b/rules/fusesoc.bzl
index bcdbb64..71f6f51 100644
--- a/rules/fusesoc.bzl
+++ b/rules/fusesoc.bzl
@@ -32,8 +32,9 @@
         outputs.extend(deps)
         groups[group] = depset(deps)
 
-    verilator_options = ctx.attr.verilator_options[BuildSettingInfo].value
-    flags.append("--verilator_options={}".format(" ".join(verilator_options)))
+    if ctx.attr.verilator_options:
+        verilator_options = ctx.attr.verilator_options[BuildSettingInfo].value
+        flags.append("--verilator_options={}".format(" ".join(verilator_options)))
 
     ctx.actions.run(
         mnemonic = "FuseSoC",