[dv/clkmgr] Enhance reset handling for stress test
Avoid most checking during reset.
Signed-off-by: Guillermo Maturana <maturana@google.com>
diff --git a/hw/ip/clkmgr/dv/env/clkmgr_if.sv b/hw/ip/clkmgr/dv/env/clkmgr_if.sv
index 788abfb..5d7a4e5 100644
--- a/hw/ip/clkmgr/dv/env/clkmgr_if.sv
+++ b/hw/ip/clkmgr/dv/env/clkmgr_if.sv
@@ -7,7 +7,9 @@
interface clkmgr_if (
input logic clk,
input logic rst_n,
- input logic rst_main_n
+ input logic rst_io_n,
+ input logic rst_main_n,
+ input logic rst_usb_n
);
import clkmgr_env_pkg::*;
@@ -141,16 +143,20 @@
logic [PIPELINE_DEPTH-1:0] clk_enable_div4_ffs;
logic [PIPELINE_DEPTH-1:0] clk_hint_otbn_div4_ffs;
logic [PIPELINE_DEPTH-1:0] ip_clk_en_div4_ffs;
- always @(posedge clocks_o.clk_io_div4_powerup) begin
- if (rst_n) begin
+ always @(posedge clocks_o.clk_io_div4_powerup or negedge rst_io_n) begin
+ if (rst_io_n) begin
clk_enable_div4_ffs <= {clk_enable_div4_ffs[PIPELINE_DEPTH-2:0], clk_enables.io_div4_peri_en};
clk_hint_otbn_div4_ffs <= {
clk_hint_otbn_div4_ffs[PIPELINE_DEPTH-2:0], clk_hints[TransOtbnIoDiv4]
};
ip_clk_en_div4_ffs <= {ip_clk_en_div4_ffs[PIPELINE_DEPTH-2:0], pwr_i.ip_clk_en};
+ end else begin
+ clk_enable_div4_ffs <= '0;
+ clk_hint_otbn_div4_ffs <= '0;
+ ip_clk_en_div4_ffs <= '0;
end
end
- clocking peri_div4_cb @(posedge clocks_o.clk_io_div4_powerup);
+ clocking peri_div4_cb @(posedge clocks_o.clk_io_div4_powerup or negedge rst_io_n);
input ip_clk_en = ip_clk_en_div4_ffs[PIPELINE_DEPTH-1];
input clk_enable = clk_enable_div4_ffs[PIPELINE_DEPTH-1];
input clk_hint_otbn = clk_hint_otbn_div4_ffs[PIPELINE_DEPTH-1];
@@ -159,39 +165,48 @@
logic [PIPELINE_DEPTH-1:0] clk_enable_div2_ffs;
logic [PIPELINE_DEPTH-1:0] ip_clk_en_div2_ffs;
- always @(posedge clocks_o.clk_io_div2_powerup) begin
- if (rst_n) begin
+ always @(posedge clocks_o.clk_io_div2_powerup or negedge rst_io_n) begin
+ if (rst_io_n) begin
clk_enable_div2_ffs <= {clk_enable_div2_ffs[PIPELINE_DEPTH-2:0], clk_enables.io_div2_peri_en};
ip_clk_en_div2_ffs <= {ip_clk_en_div2_ffs[PIPELINE_DEPTH-2:0], pwr_i.ip_clk_en};
+ end else begin
+ clk_enable_div2_ffs <= '0;
+ ip_clk_en_div2_ffs <= '0;
end
end
- clocking peri_div2_cb @(posedge clocks_o.clk_io_div2_powerup);
+ clocking peri_div2_cb @(posedge clocks_o.clk_io_div2_powerup or negedge rst_io_n);
input ip_clk_en = ip_clk_en_div2_ffs[PIPELINE_DEPTH-1];
input clk_enable = clk_enable_div2_ffs[PIPELINE_DEPTH-1];
endclocking
logic [PIPELINE_DEPTH-1:0] clk_enable_io_ffs;
logic [PIPELINE_DEPTH-1:0] ip_clk_en_io_ffs;
- always @(posedge clocks_o.clk_io_powerup) begin
- if (rst_n) begin
+ always @(posedge clocks_o.clk_io_powerup or negedge rst_io_n) begin
+ if (rst_io_n) begin
clk_enable_io_ffs <= {clk_enable_io_ffs[PIPELINE_DEPTH-2:0], clk_enables.io_peri_en};
ip_clk_en_io_ffs <= {ip_clk_en_io_ffs[PIPELINE_DEPTH-2:0], pwr_i.ip_clk_en};
+ end else begin
+ clk_enable_io_ffs <= '0;
+ ip_clk_en_io_ffs <= '0;
end
end
- clocking peri_io_cb @(posedge clocks_o.clk_io_powerup);
+ clocking peri_io_cb @(posedge clocks_o.clk_io_powerup or negedge rst_io_n);
input ip_clk_en = ip_clk_en_io_ffs[PIPELINE_DEPTH-1];
input clk_enable = clk_enable_io_ffs[PIPELINE_DEPTH-1];
endclocking
logic [PIPELINE_DEPTH-1:0] clk_enable_usb_ffs;
logic [PIPELINE_DEPTH-1:0] ip_clk_en_usb_ffs;
- always @(posedge clocks_o.clk_usb_powerup) begin
- if (rst_n) begin
+ always @(posedge clocks_o.clk_usb_powerup or negedge rst_usb_n) begin
+ if (rst_usb_n) begin
clk_enable_usb_ffs <= {clk_enable_usb_ffs[PIPELINE_DEPTH-2:0], clk_enables.usb_peri_en};
ip_clk_en_usb_ffs <= {ip_clk_en_usb_ffs[PIPELINE_DEPTH-2:0], pwr_i.ip_clk_en};
+ end else begin
+ clk_enable_usb_ffs <= '0;
+ ip_clk_en_usb_ffs <= '0;
end
end
- clocking peri_usb_cb @(posedge clocks_o.clk_usb_powerup);
+ clocking peri_usb_cb @(posedge clocks_o.clk_usb_powerup or negedge rst_usb_n);
input ip_clk_en = ip_clk_en_usb_ffs[PIPELINE_DEPTH-1];
input clk_enable = clk_enable_usb_ffs[PIPELINE_DEPTH-1];
endclocking
@@ -199,13 +214,16 @@
// Pipelining and clocking block for transactional unit clocks.
logic [PIPELINE_DEPTH-1:0][NUM_TRANS-1:0] clk_hints_ffs;
logic [PIPELINE_DEPTH-1:0] trans_clk_en_ffs;
- always @(posedge clocks_o.clk_main_powerup) begin
- if (rst_n) begin
+ always @(posedge clocks_o.clk_main_powerup or negedge rst_main_n) begin
+ if (rst_main_n) begin
clk_hints_ffs <= {clk_hints_ffs[PIPELINE_DEPTH-2:0], clk_hints};
trans_clk_en_ffs <= {trans_clk_en_ffs[PIPELINE_DEPTH-2:0], pwr_i.ip_clk_en};
+ end else begin
+ clk_hints_ffs <= '0;
+ trans_clk_en_ffs <= '0;
end
end
- clocking trans_cb @(posedge clocks_o.clk_main_powerup);
+ clocking trans_cb @(posedge clocks_o.clk_main_powerup or negedge rst_main_n);
input ip_clk_en = trans_clk_en_ffs[PIPELINE_DEPTH-1];
input clk_hints = clk_hints_ffs[PIPELINE_DEPTH-1];
input idle_i;
@@ -224,6 +242,8 @@
always @(posedge clk) begin
if (rst_n) begin
step_down_ff <= ast_clk_byp_ack == lc_ctrl_pkg::On;
+ end else begin
+ step_down_ff <= 1'b0;
end
end
clocking step_down_cb @(posedge clk);
diff --git a/hw/ip/clkmgr/dv/env/clkmgr_scoreboard.sv b/hw/ip/clkmgr/dv/env/clkmgr_scoreboard.sv
index b4bf9f3..9700946 100644
--- a/hw/ip/clkmgr/dv/env/clkmgr_scoreboard.sv
+++ b/hw/ip/clkmgr/dv/env/clkmgr_scoreboard.sv
@@ -149,17 +149,24 @@
end
endfunction
+ // Clock monitors.
+ // Notice the clock gating condition is sampled at the clock edge from clocking blocks,
+ // but we add a #0 before the actual clock is checked. This is to be certain the clock
+ // has assumed its value in case some logic needs to settle.
+
task monitor_div4_peri_clock();
forever
@cfg.clkmgr_vif.peri_div4_cb begin
- logic enable = cfg.clkmgr_vif.peri_div4_cb.clk_enable;
- logic clk_en = cfg.clkmgr_vif.peri_div4_cb.ip_clk_en;
- logic scan_en = cfg.clkmgr_vif.scanmode_i == lc_ctrl_pkg::On;
- logic gating_condition = enable && clk_en || scan_en;
- #0;
- check_clock("div4", gating_condition, cfg.clkmgr_vif.clocks_o.clk_io_div4_peri);
- if (cfg.en_cov) begin
- cov.peri_cg_wrap[PeriDiv4].sample(enable, clk_en, scan_en);
+ if (cfg.io_clk_rst_vif.rst_n) begin
+ logic enable = cfg.clkmgr_vif.peri_div4_cb.clk_enable;
+ logic clk_en = cfg.clkmgr_vif.peri_div4_cb.ip_clk_en;
+ logic scan_en = cfg.clkmgr_vif.scanmode_i == lc_ctrl_pkg::On;
+ logic gating_condition = enable && clk_en || scan_en;
+ #0;
+ check_clock("div4", gating_condition, cfg.clkmgr_vif.clocks_o.clk_io_div4_peri);
+ if (cfg.en_cov) begin
+ cov.peri_cg_wrap[PeriDiv4].sample(enable, clk_en, scan_en);
+ end
end
end
endtask
@@ -167,14 +174,16 @@
task monitor_div2_peri_clock();
forever
@cfg.clkmgr_vif.peri_div2_cb begin
- logic enable = cfg.clkmgr_vif.peri_div2_cb.clk_enable;
- logic clk_en = cfg.clkmgr_vif.peri_div2_cb.ip_clk_en;
- logic scan_en = cfg.clkmgr_vif.scanmode_i == lc_ctrl_pkg::On;
- logic gating_condition = enable && clk_en || scan_en;
- #0;
- check_clock("div2", gating_condition, cfg.clkmgr_vif.clocks_o.clk_io_div2_peri);
- if (cfg.en_cov) begin
- cov.peri_cg_wrap[PeriDiv2].sample(enable, clk_en, scan_en);
+ if (cfg.io_clk_rst_vif.rst_n) begin
+ logic enable = cfg.clkmgr_vif.peri_div2_cb.clk_enable;
+ logic clk_en = cfg.clkmgr_vif.peri_div2_cb.ip_clk_en;
+ logic scan_en = cfg.clkmgr_vif.scanmode_i == lc_ctrl_pkg::On;
+ logic gating_condition = enable && clk_en || scan_en;
+ #0;
+ check_clock("div2", gating_condition, cfg.clkmgr_vif.clocks_o.clk_io_div2_peri);
+ if (cfg.en_cov) begin
+ cov.peri_cg_wrap[PeriDiv2].sample(enable, clk_en, scan_en);
+ end
end
end
endtask
@@ -182,14 +191,16 @@
task monitor_io_peri_clock();
forever
@cfg.clkmgr_vif.peri_io_cb begin
- logic enable = cfg.clkmgr_vif.peri_io_cb.clk_enable;
- logic clk_en = cfg.clkmgr_vif.peri_io_cb.ip_clk_en;
- logic scan_en = cfg.clkmgr_vif.scanmode_i == lc_ctrl_pkg::On;
- logic gating_condition = enable && clk_en || scan_en;
- #0;
- check_clock("io", gating_condition, cfg.clkmgr_vif.clocks_o.clk_io_peri);
- if (cfg.en_cov) begin
- cov.peri_cg_wrap[PeriIo].sample(enable, clk_en, scan_en);
+ if (cfg.io_clk_rst_vif.rst_n) begin
+ logic enable = cfg.clkmgr_vif.peri_io_cb.clk_enable;
+ logic clk_en = cfg.clkmgr_vif.peri_io_cb.ip_clk_en;
+ logic scan_en = cfg.clkmgr_vif.scanmode_i == lc_ctrl_pkg::On;
+ logic gating_condition = enable && clk_en || scan_en;
+ #0;
+ check_clock("io", gating_condition, cfg.clkmgr_vif.clocks_o.clk_io_peri);
+ if (cfg.en_cov) begin
+ cov.peri_cg_wrap[PeriIo].sample(enable, clk_en, scan_en);
+ end
end
end
endtask
@@ -197,14 +208,16 @@
task monitor_usb_peri_clock();
forever
@cfg.clkmgr_vif.peri_usb_cb begin
- logic enable = cfg.clkmgr_vif.peri_usb_cb.clk_enable;
- logic clk_en = cfg.clkmgr_vif.peri_usb_cb.ip_clk_en;
- logic scan_en = cfg.clkmgr_vif.scanmode_i == lc_ctrl_pkg::On;
- logic gating_condition = enable && clk_en || scan_en;
- #0;
- check_clock("usb", gating_condition, cfg.clkmgr_vif.clocks_o.clk_usb_peri);
- if (cfg.en_cov) begin
- cov.peri_cg_wrap[PeriUsb].sample(enable, clk_en, scan_en);
+ if (cfg.usb_clk_rst_vif.rst_n) begin
+ logic enable = cfg.clkmgr_vif.peri_usb_cb.clk_enable;
+ logic clk_en = cfg.clkmgr_vif.peri_usb_cb.ip_clk_en;
+ logic scan_en = cfg.clkmgr_vif.scanmode_i == lc_ctrl_pkg::On;
+ logic gating_condition = enable && clk_en || scan_en;
+ #0;
+ check_clock("usb", gating_condition, cfg.clkmgr_vif.clocks_o.clk_usb_peri);
+ if (cfg.en_cov) begin
+ cov.peri_cg_wrap[PeriUsb].sample(enable, clk_en, scan_en);
+ end
end
end
endtask
@@ -214,48 +227,51 @@
src_e src = cfg.trans_to_src[trans];
forever begin
- logic hint, idle, clk_en, scan_en, gating_condition;
+ logic hint, idle, clk_en, scan_en, src_rst_n, gating_condition;
// Wait for the correct clocking block (to ensure that we sample when the output clock should
// be high if enabled), then read the relevant signals from that clocking block.
case (src)
SrcMain: begin
@(cfg.clkmgr_vif.trans_cb);
- hint = cfg.clkmgr_vif.trans_cb.clk_hints[trans_index];
- idle = cfg.clkmgr_vif.trans_cb.idle_i[trans_index];
+ hint = cfg.clkmgr_vif.trans_cb.clk_hints[trans_index];
+ idle = cfg.clkmgr_vif.trans_cb.idle_i[trans_index];
clk_en = cfg.clkmgr_vif.trans_cb.ip_clk_en;
+ src_rst_n = cfg.main_clk_rst_vif.rst_n;
end
SrcIoDiv4: begin
@(cfg.clkmgr_vif.peri_div4_cb);
- hint = cfg.clkmgr_vif.peri_div4_cb.clk_hint_otbn;
- idle = cfg.clkmgr_vif.peri_div4_cb.otbn_idle;
+ hint = cfg.clkmgr_vif.peri_div4_cb.clk_hint_otbn;
+ idle = cfg.clkmgr_vif.peri_div4_cb.otbn_idle;
clk_en = cfg.clkmgr_vif.peri_div4_cb.ip_clk_en;
+ src_rst_n = cfg.io_clk_rst_vif.rst_n;
end
endcase
+ if (src_rst_n) begin
+ scan_en = cfg.clkmgr_vif.scanmode_i == lc_ctrl_pkg::On;
+ gating_condition = (hint || !idle) && clk_en || scan_en;
- scan_en = cfg.clkmgr_vif.scanmode_i == lc_ctrl_pkg::On;
- gating_condition = (hint || !idle) && clk_en || scan_en;
-
- #0;
- case (trans)
- TransAes: begin
- check_clock(trans.name(), gating_condition, cfg.clkmgr_vif.clocks_o.clk_main_aes);
+ #0;
+ case (trans)
+ TransAes: begin
+ check_clock(trans.name(), gating_condition, cfg.clkmgr_vif.clocks_o.clk_main_aes);
+ end
+ TransHmac: begin
+ check_clock(trans.name(), gating_condition, cfg.clkmgr_vif.clocks_o.clk_main_hmac);
+ end
+ TransKmac: begin
+ check_clock(trans.name(), gating_condition, cfg.clkmgr_vif.clocks_o.clk_main_kmac);
+ end
+ TransOtbnIoDiv4: begin
+ check_clock(trans.name(), gating_condition, cfg.clkmgr_vif.clocks_o.clk_io_div4_otbn);
+ end
+ TransOtbnMain: begin
+ check_clock(trans.name(), gating_condition, cfg.clkmgr_vif.clocks_o.clk_main_otbn);
+ end
+ endcase
+ if (cfg.en_cov) begin
+ cov.trans_cg_wrap[trans].sample(hint, clk_en, scan_en, idle);
end
- TransHmac: begin
- check_clock(trans.name(), gating_condition, cfg.clkmgr_vif.clocks_o.clk_main_hmac);
- end
- TransKmac: begin
- check_clock(trans.name(), gating_condition, cfg.clkmgr_vif.clocks_o.clk_main_kmac);
- end
- TransOtbnIoDiv4: begin
- check_clock(trans.name(), gating_condition, cfg.clkmgr_vif.clocks_o.clk_io_div4_otbn);
- end
- TransOtbnMain: begin
- check_clock(trans.name(), gating_condition, cfg.clkmgr_vif.clocks_o.clk_main_otbn);
- end
- endcase
- if (cfg.en_cov) begin
- cov.trans_cg_wrap[trans].sample(hint, clk_en, scan_en, idle);
end
end
endtask
@@ -270,15 +286,17 @@
UVM_MEDIUM)
prev_lc_clk_byp_req = cfg.clkmgr_vif.lc_clk_byp_req;
end
- if (((cfg.clkmgr_vif.extclk_cb.extclk_sel == On) &&
- (cfg.clkmgr_vif.extclk_cb.lc_dft_en_i == On)) ||
- (cfg.clkmgr_vif.extclk_cb.lc_clk_byp_req == On)) begin
- `DV_CHECK_EQ(cfg.clkmgr_vif.ast_clk_byp_req, On, "Expected ast_clk_byp_req to be On")
- end
- if (cfg.en_cov) begin
- cov.extclk_cg.sample(cfg.clkmgr_vif.extclk_cb.extclk_sel,
- cfg.clkmgr_vif.extclk_cb.lc_dft_en_i,
- cfg.clkmgr_vif.extclk_cb.lc_clk_byp_req, cfg.clkmgr_vif.scanmode_i);
+ if (cfg.clk_rst_vif.rst_n) begin
+ if (((cfg.clkmgr_vif.extclk_cb.extclk_sel == On) &&
+ (cfg.clkmgr_vif.extclk_cb.lc_dft_en_i == On)) ||
+ (cfg.clkmgr_vif.extclk_cb.lc_clk_byp_req == On)) begin
+ `DV_CHECK_EQ(cfg.clkmgr_vif.ast_clk_byp_req, On, "Expected ast_clk_byp_req to be On")
+ end
+ if (cfg.en_cov) begin
+ cov.extclk_cg.sample(
+ cfg.clkmgr_vif.extclk_cb.extclk_sel, cfg.clkmgr_vif.extclk_cb.lc_dft_en_i,
+ cfg.clkmgr_vif.extclk_cb.lc_clk_byp_req, cfg.clkmgr_vif.scanmode_i);
+ end
end
end
endtask
@@ -286,12 +304,21 @@
task monitor_clk_dividers();
clock_dividers dividers = new();
clock_dividers::div_step_e prev_div_step = clock_dividers::DivStepUp;
+ // This controls the window for checking divided clocks. We open it after the
+ // first increment, and close it upon reset. Needed for tests that reset.
+ // May not be needed anymore since we reset the expected activity on reset
+ // active.
+ bit ok_to_check_dividers = 1'b0;
#1;
cfg.io_clk_rst_vif.wait_for_reset();
fork
forever
- @(posedge cfg.io_clk_rst_vif.rst_n) begin : handle_dividers_reset
+ @(negedge cfg.io_clk_rst_vif.rst_n) begin : handle_dividers_reset_start
+ ok_to_check_dividers = 1'b0;
+ end
+ forever
+ @(posedge cfg.io_clk_rst_vif.rst_n) begin : handle_dividers_reset_done
dividers.reset();
`uvm_info(`gfn, $sformatf("Reset divided clocks: %0s", dividers.show()), UVM_MEDIUM)
end
@@ -319,7 +346,7 @@
// Compare divided clocks, always based on values from clocking block (thus preponed).
forever
@cfg.clkmgr_vif.div_clks_cb begin : check_clocks
- if (cfg.io_clk_rst_vif.rst_n) begin
+ if (cfg.io_clk_rst_vif.rst_n && ok_to_check_dividers) begin
`DV_CHECK_EQ(cfg.clkmgr_vif.div_clks_cb.actual_clk_io_div4,
cfg.clkmgr_vif.div_clks_cb.exp_clk_io_div4, $sformatf(
"Mismatch for clk_io_div4_powerup, expected %b, got %b",
@@ -360,6 +387,10 @@
.actual_div2_value(cfg.clkmgr_vif.clocks_o.clk_io_div2_powerup),
.exp_div4_value(dividers.get_div4_clk()),
.actual_div4_value(cfg.clkmgr_vif.clocks_o.clk_io_div4_powerup));
+ if (ok_to_check_dividers == 1'b0) begin
+ ok_to_check_dividers = 1'b1;
+ `uvm_info(`gfn, "Ready to start checking divided clocks", UVM_LOW)
+ end
end else begin
`uvm_info(`gfn, "Clearing expectations because io rst_n is active", UVM_LOW)
// verilog_format: off // the args are aligned to the function parenthesis
@@ -409,6 +440,9 @@
// - For read, update predication at address phase and compare at data phase.
case (csr.get_name())
// add individual case item for each csr
+ "alert_test": begin
+ // FIXME
+ end
"intr_state": begin
// FIXME
do_read_check = 1'b0;
diff --git a/hw/ip/clkmgr/dv/env/seq_lib/clkmgr_base_vseq.sv b/hw/ip/clkmgr/dv/env/seq_lib/clkmgr_base_vseq.sv
index 7ed6160..537ae6d 100644
--- a/hw/ip/clkmgr/dv/env/seq_lib/clkmgr_base_vseq.sv
+++ b/hw/ip/clkmgr/dv/env/seq_lib/clkmgr_base_vseq.sv
@@ -61,9 +61,6 @@
!(extclk_sel_other inside {On, Off});
}
- // various knobs to enable certain routines
- bit do_clkmgr_init = 1'b1;
-
`uvm_object_new
function void post_randomize();
@@ -80,15 +77,16 @@
// These are independent: do them in parallel since pre_start consumes time.
fork
begin
- cfg.clkmgr_vif.init(.idle('1), .ip_clk_en(ip_clk_en), .scanmode(scanmode), .lc_dft_en(Off));
+ cfg.clkmgr_vif.init(.idle('1), .ip_clk_en(1'b0), .scanmode(scanmode), .lc_dft_en(Off));
+ update_csrs_with_reset_values();
end
- if (do_clkmgr_init) clkmgr_init();
+ clkmgr_init();
super.pre_start();
join
endtask
virtual task dut_init(string reset_kind = "HARD");
- super.dut_init();
+ super.dut_init(reset_kind);
endtask
virtual task dut_shutdown();
diff --git a/hw/ip/clkmgr/dv/env/seq_lib/clkmgr_extclk_vseq.sv b/hw/ip/clkmgr/dv/env/seq_lib/clkmgr_extclk_vseq.sv
index d187e31..3e71060 100644
--- a/hw/ip/clkmgr/dv/env/seq_lib/clkmgr_extclk_vseq.sv
+++ b/hw/ip/clkmgr/dv/env/seq_lib/clkmgr_extclk_vseq.sv
@@ -49,7 +49,6 @@
rand int cycles_before_ast_clk_byp_ack;
rand int cycles_before_next_trans;
- constraint trans_large_c {num_trans == 16;}
constraint cycles_to_stim_c {
cycles_before_extclk_sel inside {[4 : 20]};
cycles_before_lc_clk_byp_req inside {[4 : 20]};
diff --git a/hw/ip/clkmgr/dv/env/seq_lib/clkmgr_peri_vseq.sv b/hw/ip/clkmgr/dv/env/seq_lib/clkmgr_peri_vseq.sv
index 7347f16..20333ef 100644
--- a/hw/ip/clkmgr/dv/env/seq_lib/clkmgr_peri_vseq.sv
+++ b/hw/ip/clkmgr/dv/env/seq_lib/clkmgr_peri_vseq.sv
@@ -26,5 +26,8 @@
flipped_enables = initial_enables ^ ((1 << ral.clk_enables.get_n_bits()) - 1);
csr_wr(.ptr(ral.clk_enables), .value(flipped_enables));
end
+ // And set it back to the reset value for stress tests.
+ cfg.clk_rst_vif.wait_clks(1);
+ csr_wr(.ptr(ral.clk_enables), .value(ral.clk_enables.get_reset()));
endtask : body
endclass : clkmgr_peri_vseq
diff --git a/hw/ip/clkmgr/dv/env/seq_lib/clkmgr_smoke_vseq.sv b/hw/ip/clkmgr/dv/env/seq_lib/clkmgr_smoke_vseq.sv
index c42a627..92e4622 100644
--- a/hw/ip/clkmgr/dv/env/seq_lib/clkmgr_smoke_vseq.sv
+++ b/hw/ip/clkmgr/dv/env/seq_lib/clkmgr_smoke_vseq.sv
@@ -10,7 +10,6 @@
constraint enable_ip_clk_en {ip_clk_en == 1'b1;}
constraint all_busy {idle == '0;}
- constraint scanmode_off {sel_scanmode == LcTxTSelOff;}
task body();
update_csrs_with_reset_values();
@@ -28,11 +27,17 @@
csr_rd(.ptr(ral.clk_enables), .value(value));
flipped_value = value ^ ((1 << ral.clk_enables.get_n_bits()) - 1);
csr_wr(.ptr(ral.clk_enables), .value(flipped_value));
+
+ // And set it back to the reset value for stress tests.
+ cfg.clk_rst_vif.wait_clks(1);
+ csr_wr(.ptr(ral.clk_enables), .value(ral.clk_enables.get_reset()));
endtask : test_peri_clocks
- // Starts with all units busy, and for each one this clears the hint and reads the
- // hint status, expecting it to remain at 1 since the unit is busy; then it sets
- // the corresponding idle bit and reads status again, expecting it to be low.
+ // Starts with all units busy, and for each one this clears the hint and reads the hint status,
+ // expecting it to remain at 1 since the unit is busy; then it sets the corresponding idle bit
+ // and reads status again, expecting it to be low.
+ //
+ // We disable the value checks when reset is active since the reads return unpredictable data.
task test_trans_clocks();
trans_e trans;
logic bit_value;
@@ -60,9 +65,10 @@
`uvm_info(`gfn, $sformatf("Clearing %s hint bit", descriptor.unit.name), UVM_MEDIUM)
csr_wr(.ptr(descriptor.hint_bit), .value(1'b0));
csr_rd(.ptr(descriptor.value_bit), .value(bit_value));
- `DV_CHECK_EQ(bit_value, 1'b1, $sformatf(
- "%s hint value cannot drop while busy", descriptor.unit.name()))
-
+ if (!cfg.under_reset) begin
+ `DV_CHECK_EQ(bit_value, 1'b1, $sformatf(
+ "%s hint value cannot drop while busy", descriptor.unit.name()))
+ end
`uvm_info(`gfn, $sformatf("Setting %s idle bit", descriptor.unit.name), UVM_MEDIUM)
cfg.clk_rst_vif.wait_clks(1);
idle[trans] = 1'b1;
@@ -70,10 +76,12 @@
// Some cycles for the logic to settle.
cfg.clk_rst_vif.wait_clks(3);
csr_rd(.ptr(descriptor.value_bit), .value(bit_value));
- `DV_CHECK_EQ(bit_value, 1'b0, $sformatf(
- "%s hint value should drop when idle", descriptor.unit.name()))
+ if (!cfg.under_reset) begin
+ `DV_CHECK_EQ(bit_value, 1'b0, $sformatf(
+ "%s hint value should drop when idle", descriptor.unit.name()))
+ end
trans = trans.next();
end while (trans != trans.first);
+ csr_wr(.ptr(ral.clk_hints), .value(ral.clk_hints.get_reset()));
endtask : test_trans_clocks
-
endclass : clkmgr_smoke_vseq
diff --git a/hw/ip/clkmgr/dv/env/seq_lib/clkmgr_trans_vseq.sv b/hw/ip/clkmgr/dv/env/seq_lib/clkmgr_trans_vseq.sv
index 58c0eb3..303c5e6 100644
--- a/hw/ip/clkmgr/dv/env/seq_lib/clkmgr_trans_vseq.sv
+++ b/hw/ip/clkmgr/dv/env/seq_lib/clkmgr_trans_vseq.sv
@@ -55,6 +55,7 @@
csr_rd(.ptr(ral.clk_hints_status), .value(value));
// We expect all units to be on.
`DV_CHECK_EQ(value, '1, "All idle and all hints high: units status should be high")
+ // Set hints to the reset value for stress tests.
csr_wr(.ptr(ral.clk_hints), .value(ral.clk_hints.get_reset()));
end
endtask : body
diff --git a/hw/ip/clkmgr/dv/tb.sv b/hw/ip/clkmgr/dv/tb.sv
index d0725ae..97b52a4 100644
--- a/hw/ip/clkmgr/dv/tb.sv
+++ b/hw/ip/clkmgr/dv/tb.sv
@@ -53,7 +53,9 @@
clkmgr_if clkmgr_if (
.clk(clk),
.rst_n(rst_n),
- .rst_main_n(rst_main_n)
+ .rst_io_n(rst_io_n),
+ .rst_main_n(rst_main_n),
+ .rst_usb_n(rst_usb_n)
);
initial begin
