[top / rstmgr] Top level updates to add rstmgr template

- Add top specific core files
- Update top_earlgrey.hjson

Signed-off-by: Timothy Chen <timothytim@google.com>

[top] adjust spacing

Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
index 2ff863b..34d7193 100644
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -87,22 +87,15 @@
   // Reset attributes
   // name: name of reset.
   //
-  // leaf: whether the reset is a leaf node
-  // 1: it is a leaf node and will not be used to generate other resets
-  // 0: it is not a leaf and will be used to generate other resets
-  //
-  // width: the width of a reset. A reset can be multi-bits to
-  // represent power domains
+  // gen: whether the reset is generated
+  // 1: it is a generated reset inside rstmgr
+  // 0: it is a hardwired design reset inside rstmgr (roots and por)
   //
   // type: the reset type [ext, top]
   // ext: the reset is coming in from the ports, external to earlgrey
+  // int: the reset is only used inside rstmgr
   // top: the reset is output from rstmgr to top level struct
   //
-  // inst: the cell used to generate this reset.
-  // por: generated through rstmgr_por
-  // leaf: generated through sync cell
-  // ctrl: generated through rstmgr_ctrl
-  //
   // root: The parent reset
   // If type is "ext", there is no root, since it is external
   //
@@ -110,26 +103,27 @@
   // If no domain, it means there is no choice, just inherits from root.
   // Otherwise, selects the domain to which it is related
   // 0 is defaulted for always on.
+  // TBD: This should eventually be changed to a name->index project wide lookup
   //
   // clk:  related clock domain for synchronous release
   // If type is "por", there is not related clock, since it is
   // likely external or generated from a voltage comparator
   //
   resets: [
-    { name: "rst_ni",      leaf: 0, width: 1, type: "ext"                                                  }
-    { name: "por_aon",     leaf: 0, width: 1, type: "top",              root: "rst_ni",  clk: "aon"        }
-    { name: "lc_src",      leaf: 0, width: 2, type: "top",              root: "por",     clk: "io_div2"    }
-    { name: "sys_src",     leaf: 0, width: 2, type: "top",              root: "por",     clk: "io_div2"    }
-    { name: "por",         leaf: 1, width: 1, type: "top",              root: "por_aon", clk: "main"       }
-    { name: "por_io",      leaf: 1, width: 1, type: "top",              root: "por_aon", clk: "io"         }
-    { name: "por_io_div2", leaf: 1, width: 1, type: "top",              root: "por_aon", clk: "io_div2"    }
-    { name: "por_usb",     leaf: 1, width: 1, type: "top",              root: "por_aon", clk: "usb"        }
-    { name: "lc",          leaf: 1, width: 1, type: "top", domain: "0", root: "lc_src",  clk: "io_div2"    }
-    { name: "sys",         leaf: 1, width: 1, type: "top", domain: "0", root: "sys_src", clk: "main"       }
-    { name: "sys_io",      leaf: 1, width: 1, type: "top", domain: "0", root: "sys_src", clk: "io_div2"    }
-    { name: "sys_aon",     leaf: 1, width: 1, type: "top", domain: "0", root: "sys_src", clk: "aon"        }
-    { name: "spi_device",  leaf: 1, width: 1, type: "top", domain: "0", root: "sys_src", clk: "io_div2",  sw: 1 }
-    { name: "usb",         leaf: 1, width: 1, type: "top", domain: "0", root: "sys_src", clk: "usb", sw: 1 }
+    { name: "rst_ni",      gen: 0, type: "ext"                                                  }
+    { name: "por_aon",     gen: 0, type: "top",              root: "rst_ni",  clk: "aon"        }
+    { name: "lc_src",      gen: 0, type: "int",              root: "por",     clk: "io_div2"    }
+    { name: "sys_src",     gen: 0, type: "int",              root: "por",     clk: "io_div2"    }
+    { name: "por",         gen: 1, type: "top",              root: "por_aon", clk: "main"       }
+    { name: "por_io",      gen: 1, type: "top",              root: "por_aon", clk: "io"         }
+    { name: "por_io_div2", gen: 1, type: "top",              root: "por_aon", clk: "io_div2"    }
+    { name: "por_usb",     gen: 1, type: "top",              root: "por_aon", clk: "usb"        }
+    { name: "lc",          gen: 1, type: "top", domain: "0", root: "lc_src",  clk: "io_div2"    }
+    { name: "sys",         gen: 1, type: "top", domain: "0", root: "sys_src", clk: "main"       }
+    { name: "sys_io",      gen: 1, type: "top", domain: "0", root: "sys_src", clk: "io_div2"    }
+    { name: "sys_aon",     gen: 1, type: "top", domain: "0", root: "sys_src", clk: "aon"        }
+    { name: "spi_device",  gen: 1, type: "top", domain: "0", root: "sys_src", clk: "io_div2", sw: 1 }
+    { name: "usb",         gen: 1, type: "top", domain: "0", root: "sys_src", clk: "usb",     sw: 1 }
   ]
 
   // Number of cores: used in rv_plic and timer
diff --git a/hw/top_earlgrey/ip/rstmgr/rstmgr.core b/hw/top_earlgrey/ip/rstmgr/rstmgr.core
index e564131..9a1689d 100644
--- a/hw/top_earlgrey/ip/rstmgr/rstmgr.core
+++ b/hw/top_earlgrey/ip/rstmgr/rstmgr.core
@@ -2,7 +2,7 @@
 # Copyright lowRISC contributors.
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:top:rstmgr:0.1"
+name: "lowrisc:systems:rstmgr:0.1"
 description: "Top level Reset Manager"
 
 filesets:
diff --git a/hw/top_earlgrey/ip/rstmgr/rstmgr_pkg.core b/hw/top_earlgrey/ip/rstmgr/rstmgr_pkg.core
index 543dfd5..19c4796 100644
--- a/hw/top_earlgrey/ip/rstmgr/rstmgr_pkg.core
+++ b/hw/top_earlgrey/ip/rstmgr/rstmgr_pkg.core
@@ -2,13 +2,12 @@
 # Copyright lowRISC contributors.
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:top:rstmgr_pkg:0.1"
+name: "lowrisc:systems:rstmgr_pkg:0.1"
 description: "Top level Reset Manager Package"
 
 filesets:
   files_rtl:
     depend:
-      - lowrisc:ip:pwrmgr_only_reg
       - lowrisc:ip:pwrmgr_pkg
       - lowrisc:ip:rstmgr_reg
     files:
diff --git a/hw/top_earlgrey/ip/rstmgr/rstmgr_reg.core b/hw/top_earlgrey/ip/rstmgr/rstmgr_reg.core
index 94a7bb9..b8a4b62 100644
--- a/hw/top_earlgrey/ip/rstmgr/rstmgr_reg.core
+++ b/hw/top_earlgrey/ip/rstmgr/rstmgr_reg.core
@@ -2,7 +2,7 @@
 # Copyright lowRISC contributors.
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:top:rstmgr_reg:0.1"
+name: "lowrisc:systems:rstmgr_reg:0.1"
 description: "Top level rstmgr registers"
 
 filesets:
diff --git a/hw/top_earlgrey/top_earlgrey.core b/hw/top_earlgrey/top_earlgrey.core
index 5255e48..80d189c 100644
--- a/hw/top_earlgrey/top_earlgrey.core
+++ b/hw/top_earlgrey/top_earlgrey.core
@@ -27,7 +27,6 @@
       - lowrisc:ip:otbn
       - lowrisc:prim:ram_1p_adv
       - lowrisc:prim:rom_adv
-      - lowrisc:ip:rstmgr
       - lowrisc:prim:flash
       - lowrisc:ip:flash_ctrl:0.1
       - lowrisc:constants:top_pkg
@@ -35,7 +34,7 @@
       - lowrisc:ip:usbdev
       - lowrisc:top_earlgrey:xbar_main
       - lowrisc:top_earlgrey:xbar_peri
-      - lowrisc:ip:rstmgr
+      - lowrisc:systems:rstmgr
       - lowrisc:ip:pwrmgr
       - lowrisc:systems:sensor_ctrl
       - lowrisc:systems:ast_wrapper_pkg